# US 2024/0203993 A1 · Low resistance metalization for connecting a vertical transport fet single-cpp inverter

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- Number: US 2024/0203993 A1
- Document ID: US20240203993A1
- Status: Published application
- Kind: A1
- Application number: 18/065,663
- Filed: 2022-12-14
- Published: 2024-06-20
- Earliest claimed: 2022-12-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Nicholas Anthony Lanzillo; Albert M. Chu; Ruilong Xie; Lawrence A. Clevenger
- Web page: https://patentgrep.com/patent/US20240203993A1

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 84/837: {comprising vertical IGFETs}
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a first transistor, a second transistor, and a contact element. The first transistor includes a first source or drain (S/D). The second transistor includes a second S/D and a gate. The contact element includes substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.

## Claims

### Claim 1

A multi-layer integrated circuit (IC) structure comprising:
a first transistor having a first source or drain (S/D);
a second transistor having a second S/D and a gate; and
a contact element having substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the contact element is within one metallization layer of the IC structure.

### Claim 3 (depends on 2)

The IC structure of claim 2, wherein the contact element is in a middle-of-line (MOL) region of the IC structure.

### Claim 4 (depends on 1)

The IC structure of claim 1, wherein:
the first transistor comprises a first n-type field effect transistor (NFET), a first p-type FET (PFET), and a first shared gate; and
the first S/D region comprises:
a S/D region of the first NFET; and
a S/D region of the first PFET.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein:
the second transistor comprises a second NFET, a second PFET, and a second shared gate; and
the gate comprises the second shared gate.

### Claim 6 (depends on 5)

The IC structure of claim 5, wherein the contact element connects:
the S/D region of the first NFET;
the S/D region of the first PFET; and
the second shared gate.

### Claim 7 (depends on 1)

The IC structure of claim 1 further comprising an inverter comprising the first transistor and the second transistor.

### Claim 8 (depends on 7)

The IC structure of claim 7, wherein:
the first transistor comprises a first vertical transport field effect transistor (VTFET);
the second transistor comprises a second VTFET; and
the first VTFET is separated from the second VTFET by one transistor gate pitch.

### Claim 9 (depends on 8)

The IC structure of claim 8 further comprising:
a S/D contact in electrical contact with the first S/D, wherein the S/D contact is within a first metallization level; and
a gate contact in electrical contact with the gate, wherein the gate contact is within the first metallization level.

### Claim 10 (depends on 9)

The IC structure of claim 9, wherein:
the contact element electrically couples to the first S/D through the S/D contact;
the contact element electrically couples to the gate through the gate contact; and
the one metallization level is adjacent the first metallization level.

### Claim 11

A method of forming a multi-layer integrated circuit (IC) structure, the method comprising:
forming a first transistor having a first source or drain (S/D);
forming a second transistor having a second S/D and a gate; and
forming a contact element having substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.

### Claim 12 (depends on 11)

The method of claim 11, wherein the contact element is within one metallization layer of the IC structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the contact element is formed in a middle-of-line (MOL) region of the IC structure.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
the first transistor comprises a first n-type field effect transistor (NFET), a first p-type FET (PFET), and a first shared gate;
the first S/D region comprises:
a S/D region of the first NFET; and
a S/D region of the first PFET;
the second transistor comprises a second NFET, a second PFET, and a second shared gate; and
the gate comprises the second shared gate.

### Claim 15 (depends on 14)

The method of claim 14, wherein the contact element connects:
the S/D region of the first NFET;
the S/D region of the first PFET; and
the second shared gate.

### Claim 16 (depends on 11)

The method of claim 11, wherein forming the contact element comprises using damascene fabrication operations and subtractive fabrication operations.

### Claim 17 (depends on 11)

The method of claim 11, wherein forming the contact element comprises:
using vertically oriented masking to form substantially vertical features of the contact element; and
using horizontally oriented masking to form the substantially horizontal features of the contact element.

### Claim 18 (depends on 11)

The method of claim 11, wherein forming the first transistor and forming the second transistor forms an inverter.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the first transistor comprises a first vertical transport field effect transistor (VTFET);
the second transistor comprise a second VTFET; and
the first VTFET is separated from the second VTFET by one transistor gate pitch.

### Claim 20 (depends on 19)

The method of claim 19 further comprising:
forming a S/D contact in electrical contact with the first S/D, wherein the S/D contact is within a first metallization level; and
forming a gate contact in electrical contact with the gate, where in the gate contact is within the first metallization level;
wherein the contact element electrically couples to the S/D through the S/D contact;
wherein the contact element electrically couples to the gate contact through the gate contact; and
wherein the one metallization level is adjacent the first metallization level.