# US 2024/0203979 A1 · Layer transfer transistor for gallium nitride (gan) integrated circuit technology

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- Number: US 2024/0203979 A1
- Document ID: US20240203979A1
- Status: Published application
- Kind: A1
- Application number: 18/085,122
- Filed: 2022-12-20
- Published: 2024-06-20
- Earliest claimed: 2022-12-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Samuel James BADER; Han Wui THEN
- Web page: https://patentgrep.com/patent/US20240203979A1

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based transistor structure is above substrate, the silicon-based transistor structure at a level above the gate of the GaN device in a region outside of the GaN device.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and
a silicon-based transistor structure above substrate, the silicon-based transistor structure at a level above the gate of the GaN device in a region outside of the GaN device.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the silicon-based transistor structure is included in a multiplexor circuit for selective addressing of the GaN device, or the GaN device is included in a multiplexor circuit for selective addressing of the silicon-based transistor structure.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the silicon-based transistor structure comprises a silicon crystal layer.

### Claim 4 (depends on 3)

The integrated circuit structure of claim 3, wherein the silicon crystal layer is bonded to a dielectric layer, the dielectric layer above the GaN device

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the silicon-based transistor structure comprises a source, a gate, and a drain.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, further comprising contacts to the GaN device and to the silicon-based transistor structure.

### Claim 7

A method of fabricating an integrated circuit structure, the method comprising:
forming a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and
forming a silicon-based transistor structure above substrate using a layer transfer process, the silicon-based transistor structure formed at a level above the gate of the GaN device in a region outside of the GaN device.

### Claim 8 (depends on 7)

The method of claim 7, wherein the silicon-based transistor structure comprises a silicon crystal layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the silicon crystal layer is bonded to a dielectric layer, the dielectric layer above the GaN device

### Claim 10 (depends on 7)

The method of claim 7, wherein the silicon-based transistor structure comprises a source, a gate, and a drain.

### Claim 11 (depends on 7)

The method of claim 7, further comprising forming contacts to the GaN device and to the silicon-based transistor structure.

### Claim 12

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and
a silicon-based transistor structure above substrate, the silicon-based transistor structure at a level above the gate of the GaN device in a region outside of the GaN device.

### Claim 13 (depends on 12)

The computing device of claim 12, further comprising:
a memory coupled to the board.

### Claim 14 (depends on 12)

The computing device of claim 12, further comprising:
a communication chip coupled to the board.

### Claim 15 (depends on 12)

The computing device of claim 12, further comprising:
a camera coupled to the board.

### Claim 16 (depends on 12)

The computing device of claim 12, wherein the component is a packaged integrated circuit die.

### Claim 17

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and
forming a silicon-based transistor structure above substrate using a layer transfer process, the silicon-based transistor structure formed at a level above the gate of the GaN device in a region outside of the GaN device.

### Claim 18 (depends on 17)

The computing device of claim 17, further comprising:
a memory coupled to the board.

### Claim 19 (depends on 17)

The computing device of claim 17, further comprising:
a communication chip coupled to the board.

### Claim 20 (depends on 17)

The computing device of claim 17, further comprising:
a camera coupled to the board.

### Claim 21 (depends on 17)

The computing device of claim 17, wherein the component is a packaged integrated circuit die.