# US 2024/0203484 A1 · Memory device

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- Number: US 2024/0203484 A1
- Document ID: US20240203484A1
- Status: Published application
- Kind: A1
- Application number: 18/459,066
- Filed: 2023-08-31
- Published: 2024-06-20
- Earliest claimed: 2022-12-20
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Kenya Tashiro
- Web page: https://patentgrep.com/patent/US20240203484A1

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A first inverter circuit including second and third transistors coupled at a third node and a second inverter circuit including fourth and fifth transistors coupled at a fourth node are coupled between first and second nodes. An eighth transistor is coupled between a gate of the third transistor and the third node. A ninth transistor is coupled between a gate of the fifth transistor and the fourth node. A state in which first and second voltages are applied to the first and second nodes is formed at a first time. A third voltage is applied to the first node at a second time. A fourth voltage is applied to the second node at a third time. The second voltage is applied to the second node at a fourth time. The first voltage is applied to the first node at a fifth time.

## Claims

### Claim 1

A memory device comprising:
a capacitor;
a first transistor that has a first end coupled to the capacitor;
a first inverter circuit that is coupled between a first node and a second node and includes a p-type second transistor and an n-type third transistor coupled in series at a third node;
a second inverter circuit that is coupled between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor coupled in series at a fourth node, the fifth transistor having a gate coupled to a second end of the first transistor;
a sixth transistor coupled between the gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node; and
a ninth transistor coupled between the gate of the fifth transistor and the fourth node, wherein
a state in which a first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node is formed at a first time, a third voltage between the second voltage and the first voltage is applied to the first node at a second time after the first time, a fourth voltage between the second voltage and the first voltage is applied to the second node at a third time after the second time, the second voltage is applied to the second node at a fourth time after the third time, and the first voltage is applied to the first node at a fifth time after the fourth time.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein
while the first voltage is applied to the first node and the second voltage is applied to the second node, a fifth voltage higher than the second voltage is kept being applied to a gate of the eighth transistor and a gate of the ninth transistor.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein
before a time at which a sixth voltage higher than the second voltage is applied to a gate of the first transistor and after the third time, the second voltage is applied to the gate of the eighth transistor and the gate of the ninth transistor.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein
from the fourth time to the fifth time, the second voltage is applied to a gate of the sixth transistor and a gate of the seventh transistor.

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein
after the fifth time, the second voltage is kept being applied to the gate of the sixth transistor and the gate of the seventh transistor.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein
while the first voltage is applied to the first node and the second voltage is applied to the second node, a fifth voltage higher than the second voltage is kept being applied to a gate of the eighth transistor and a gate of the ninth transistor.

### Claim 7 (depends on 6)

The memory device according to claim 6, wherein
before a time at which a sixth voltage higher than the second voltage is applied to a gate of the first transistor and after the third time, the second voltage is applied to the gate of the eighth transistor and the gate of the ninth transistor.

### Claim 8 (depends on 6)

The memory device according to claim 6, wherein
from a time after the third time and before the fourth time to the fifth time, the second voltage is kept being applied to the gate of the eighth transistor and the gate of the ninth transistor.

### Claim 9

A memory device comprising:
a capacitor;
a first transistor that has a first end coupled to the capacitor;
a first inverter circuit that is coupled between a first node and a second node and includes a p-type second transistor and an n-type third transistor coupled in series at a third node;
a second inverter circuit that is coupled between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor coupled in series at a fourth node, the fifth transistor having a gate coupled to a second end of the first transistor;
a sixth transistor coupled between the gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node;
a ninth transistor coupled between the gate of the fifth transistor and the fourth node;
a tenth transistor between a node of a first potential and the first node;
an eleventh transistor between the second node and a node of a second potential lower than the first potential; and
a control circuit that
receives a first signal and a second signal,
includes a delay circuit that outputs a third signal that is a delayed version of the second signal,
applies a fourth signal having a level based on the first signal, the second signal, and the third signal to a gate of the eleventh transistor, and
applies a fifth signal having a level based on the first signal and the second signal to a gate of the tenth transistor.

### Claim 10 (depends on 9)

The memory device according to claim 9, wherein
the fifth signal is not based on the first signal.

### Claim 11 (depends on 9)

The memory device according to claim 9, wherein
the control circuit includes
a first circuit that outputs the fifth signal having a second level while both of the second signal and the third signal have a first level, and
a second circuit that outputs the fourth signal having a fourth level while the first signal has a third level and one of the second signal and the third signal has the first level.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein
the first level is a high level,
the second level is a low level,
the third level is a low level, and
the fourth level is a high level.

### Claim 13 (depends on 11)

The memory device according to claim 11, wherein
the fifth signal is not based on the first signal.

### Claim 14 (depends on 11)

The memory device according to claim 11, wherein
the first circuit includes a NAND gate,
the NAND gate receives the second signal and the third signal and outputs the fifth signal,
the second circuit includes a first NOR gate and a second NOR gate,
the first NOR gate receives the second signal and the third signal and outputs a sixth signal, and
the second NOR gate receives the sixth signal and the first signal and outputs the fourth signal.

### Claim 15 (depends on 14)

The memory device according to claim 14, wherein
the first level is a high level,
the second level is a low level,
the third level is a low level, and
the fourth level is a high level.