# US 2024/0203364 A1 · Display device and display panel

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- Number: US 2024/0203364 A1
- Document ID: US20240203364A1
- Status: Published application
- Kind: A1
- Application number: 18/241,268
- Filed: 2023-09-01
- Published: 2024-06-20
- Earliest claimed: 2022-12-16
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: SungMin Park; Jinu Lee
- Web page: https://patentgrep.com/patent/US20240203364A1

## CPC

- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display panel includes a plurality of subpixels, a plurality of data lines, and a plurality of gate lines. A data driving circuit supplies a data voltage to the data lines. A gate driving circuit supplies a gate signal to the gate lines. A timing controller controls the data driving circuit and the gate driving circuit. A display area of the display panel includes a first area corresponding to the data driving circuit and a second area located outside of the first area. A first data link line group having a linear structure is connected to a first data line group disposed in the first area. A second data link line group having a bending structure is connected to a second data line group disposed in the second areas.

## Claims

### Claim 1

A display device comprising:
a display panel comprising a plurality of data lines and a plurality of gate lines;
a data driving circuit supplying a data voltage to the plurality of data lines;
wherein the display panel includes a display area;
wherein the display area includes a first area corresponding to the data driving circuit and a second area located outside the first area;
a first data link line group having a linear structure and connected to a first data line group disposed in the first area among the plurality of data lines; and
a second data link line group having a bending structure and connected to a second data line group disposed in the second areas among the plurality of data lines.

### Claim 2 (depends on 1)

The display device according to claim 1, wherein the first data link line group is disposed between the data driving circuit and the first area.

### Claim 3 (depends on 1)

The display device according to claim 1, wherein the second data link line group having a bending structure comprises:
(2−1)th data link lines extending from the data driving circuit to the first area;
(2−2)th data link lines disposed in the first area and connected to the (2−1)th data link lines; and
(2−3)th data link lines connecting the (2−2)th data link lines and the second data line group.

### Claim 4 (depends on 3)

The display device according to claim 3, wherein the (2−1)th data link lines linearly connect the data driving circuit and the (2−2)th data link lines.

### Claim 5 (depends on 3)

The display device according to claim 3, wherein the (2−2)th data link lines are disposed in parallel to the first data line group.

### Claim 6 (depends on 3)

The display device according to claim 3, wherein the (2−3)th data link lines extend from the first area in parallel to the plurality of gate lines and are linearly connected to the second data line group disposed in the second areas.

### Claim 7 (depends on 3)

The display device according to claim 3, wherein the (2−3)th data link lines are configured such that lengths thereof increase as distances from the data driving circuit increase.

### Claim 8 (depends on 3)

The display device according to claim 3, wherein the (2−3)th data link lines are provided on a different layer from the second data line group.

### Claim 9 (depends on 1)

The display device according to claim 1, further comprising dummy data link lines disposed to alternate with the data lines of the second data line group of the second areas.

### Claim 10 (depends on 3)

The display device according to claim 3, wherein the display panel further comprises a plurality of subpixels provided at intersections of the plurality of data lines and the plurality of gate lines, and
wherein each of the subpixels comprises:
a light-emitting element; and
a driving transistor supplying driving current to the light-emitting element,
wherein each of the (2−2)th data link lines is disposed to spaced away from the driving transistor or a source electrode of the driving transistor.

### Claim 11 (depends on 10)

The display device according to claim 10, wherein each of the subpixels further comprises:
a first switching transistor having a gate electrode to which a first scan signal is applied, a drain electrode connected to a gate electrode of the driving transistor, and a source electrode connected to a drain electrode of the driving transistor;
a second switching transistor having a gate electrode to which a second scan signal is applied, a source electrode to which a data voltage is applied, and a drain electrode connected to the source electrode of the driving transistor;
a third switching transistor having a gate electrode to which an emission signal is applied, a source electrode to which a high-potential driving voltage is applied through a driving voltage line, and a drain electrode connected to the source electrode of the driving transistor;
a fourth switching transistor having a gate electrode to which the emission signal is applied, a source electrode connected to the drain electrode of the driving transistor, and a drain electrode connected to an anode of the light-emitting element;
a fifth switching transistor having a gate electrode to which a fourth scan signal is applied, a drain electrode to which a stabilization voltage is supplied, and a source electrode connected to the gate electrode of the driving transistor and a storage capacitor;
a sixth switching transistor having a gate electrode to which a third scan signal is applied, a source electrode to which a reset voltage is supplied, and a drain electrode connected to the anode of the light-emitting element; and
a seventh switching transistor having a gate electrode to which a fifth scan signal is applied, a source electrode to which a bias voltage is supplied, and a drain electrode connected to the source electrode of the driving transistor.

### Claim 12 (depends on 11)

The display device according to claim 11, wherein each of the (2−2)th data link lines is disposed between the source electrode of the driving transistor and the driving voltage line, and disposed to be closer to the driving voltage line rather than the source electrode of the driving transistor.

### Claim 13 (depends on 12)

The display device according to claim 12, wherein each of the (2−2)th data link lines is disposed at a position spaced apart from the driving voltage line by a minimum processing distance.

### Claim 14

A display panel comprising:
a plurality of subpixels;
a plurality of data lines comprising a first data line group disposed in a first area corresponding to a data driving circuit and a second data line group disposed in a second area located outside the first area;
a plurality of gate lines;
a first data link line group having a linear structure and connected to the first data line group disposed in the first area; and
a second data link line group having a bending structure and connected to the second data line group disposed in the second areas.