# US 2024/0202425 A1 · Implementation of deep neural networks for testing and quality control in the production of memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0202425 A1 - Document ID: US20240202425A1 - Status: Published application - Kind: A1 - Application number: 18/586,736 - Filed: 2024-02-26 - Published: 2024-06-20 - Earliest claimed: 2019-05-10 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Cheng-Chung Chu; Janet George; Daniel J. Linnen; Ashish Ghai - Web page: https://patentgrep.com/patent/US20240202425A1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/047: Probabilistic or stochastic networks - G06N 3/0475: Generative networks - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06N 3/088: Non-supervised learning, e.g. competitive learning - G06N 3/09: Supervised learning - G06N 3/094: Adversarial learning - H05K 13/081: {Integration of optical monitoring devices in assembly lines; Processes using optical monitoring devices specially adapted for controlling devices or machines in assembly lines} - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - G06F 2119/22: Yield analysis or yield optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN). ## Claims ### Claim 1 A method, comprising: preparing multiple instances of a circuit element mounted onto one or more circuit boards; generating photographic images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards; generating artificial images of multiple instances of the circuit element mounted onto one or more circuit boards; training a neural network on a combination of the photographic images and the artificial images of multiple instances of a circuit element mounted onto one or more circuit boards; applying the trained neural network to one or more additional instances of the circuit element mounted to a circuit board; analyzing results of the application of the trained neural network to the one or more additional instances of the circuit element mounted to a circuit board; and determining whether one or more of the additional instances of the circuit element are defectively mounted to the circuit board. ### Claim 2 (depends on 1) The method of claim 1, wherein determining whether one or more of the additional instances of the circuit elements defectively mounted to the circuit board includes determining whether the determining whether one or more of the additional instances of the circuit element are mounted to the circuit board with a correct orientation. ### Claim 3 (depends on 1) The method of claim 1, wherein the circuit element is a capacitor. ### Claim 4 (depends on 1) The method of claim 1, wherein generating artificial images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards includes generating defective instances of a circuit element mounted onto one or more circuit boards. ### Claim 5 (depends on 1) The method of claim 1, wherein generating artificial images of multiple instances of the circuit element mounted onto one or more circuit boards includes generating the artificial images by a generative adversary network. ### Claim 6 (depends on 1) The method of claim 1, wherein generating the artificial images comprises: receiving random noise as an input; and generating an initial set of artificial images from the random noise. ### Claim 7 (depends on 6) The method of claim 6, wherein generating the artificial images further comprises: preforming a sorting operation of the photographic images and on the initial set of artificial images, and wherein training the neural network on the combination of the photographic images and the artificial images comprises: concurrently and competitively training neural network on the photographic images and on the initial set of artificial images. ### Claim 8 (depends on 7) The method of claim 7, wherein generating the artificial images comprises: based on concurrently and competitively training neural network on the photographic images and on the initial set of artificial images, generating an improved set of artificial images. ### Claim 9 (depends on 1) The method of claim 1, further comprising: assemble the one or more additional instances of the circuit element mounted to the circuit board. ### Claim 10 (depends on 9) The method of claim 9, wherein the one or more additional instances of the circuit element mounted to the circuit board are assembled on an assembly line, further comprising: removing the instances of the circuit element that are defectively mounted to the circuit board from the assembly line. ### Claim 11 (depends on 10) The method of claim 10, further comprising: reworking the removed instances of the circuit element. ### Claim 12 (depends on 9) The method of claim 9, further comprising modifying a process by which the one or more additional instances of the circuit element mounted to the circuit board based on the determining whether the one or more of the additional instances of the circuit element are defectively mounted to the circuit board. ### Claim 13 (depends on 1) The method of claim 1, further comprising: assemble the one or more additional instances of the circuit element mounted to the circuitry board in one or more solid state drives. ### Claim 14 (depends on 1) The method of claim 1, wherein training the neural network on the combination of the photographic images and the artificial images of multiple instances of the circuit element mounted onto one or more circuit boards comprises: training the neural network on a landmark on each of the one or more circuit boards and a marking on each of the circuit elements. ### Claim 15 A system, comprising: one or more processors, the one or more processors configured to: receive photographic images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards; generate artificial images of multiple instances of the circuit element mounted onto one or more circuit boards; train a neural network on a combination of the photographic images and the artificial images of multiple instances of a circuit element mounted onto one or more circuit boards; apply the trained neural network to one or more additional instances of the circuit element mounted to a circuit board; analyze results of the application of the trained neural network to the one or more additional instances of the circuit element mounted to a circuit board; and determine whether one or more of the additional instances of the circuit element are defectively mounted to the circuit board. ### Claim 16 (depends on 15) The system of claim 15, wherein, to determine whether one or more of the additional instances of the circuit elements defectively mounted to the circuit board, the one or more processors are further configured to: determine whether the determining whether one or more of the additional instances of the circuit element are mounted to the circuit board with a correct orientation. ### Claim 17 (depends on 15) The system of claim 15, wherein the circuit element is a capacitor. ### Claim 18 (depends on 15) The system of claim 15, wherein, to generate the artificial images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards, the one or more processors are further configured to: generate defective instances of a circuit element mounted onto one or more circuit boards. ### Claim 19 (depends on 15) The system of claim 15, wherein, to generate the artificial images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards, the one or more processors are further configured to: generate the artificial images by a generative adversary network. ### Claim 20 (depends on 15) The system of claim 15, wherein, to generate the artificial images of the prepared multiple instances of a circuit element mounted onto one or more circuit boards, the one or more processors are further configured to: receive random noise as an input; and generate an initial set of artificial images from the random noise.