# US 2024/0202145 A1 · Memory Die Interconnections to Physical Layer Interfaces

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- Number: US 2024/0202145 A1
- Document ID: US20240202145A1
- Status: Published application
- Kind: A1
- Application number: 18/540,427
- Filed: 2023-12-14
- Published: 2024-06-20
- Earliest claimed: 2022-12-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yang Lu; Kang-Yong Kim
- Web page: https://patentgrep.com/patent/US20240202145A1

## CPC

- G06F 13/1684: {using multiple buses}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4234: {being a memory bus}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

## Claims

### Claim 1

An apparatus comprising:
at least two physical interfaces (PHYs) comprising a first PHY and a second PHY, each of the at least two PHYs comprising:
a chip select (CS) bus;
a command-and-address (CA) bus; and
at least one data input/output (DQ) bus; and
at least one memory die operably coupled to:
the first PHY via the CA bus of the first PHY and the at least one DQ bus of the first PHY; and
the second PHY via the CS bus of the second PHY.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the at least one memory die comprises a first memory die and the apparatus further comprises a second memory die, the second memory die operably coupled to:
the second PHY via the CA bus of the second PHY and the at least one DQ bus of the second PHY; and
the first PHY via the CS bus of the first PHY.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a third memory die, the third memory die operably coupled to:
the first PHY via the CA bus of the first PHY, the at least one DQ bus of the first PHY, and the CS bus of the first PHY; or
the second PHY via the CA bus of the second PHY, the at least one DQ bus of the second PHY, and the CS bus of the second PHY.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the at least one memory die is not coupled to:
the first PHY via the CS bus of the first PHY; or
the second PHY via the CA bus of the second PHY and the at least one DQ bus of the second PHY.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the CS bus is configured as an L-bit bus in which ‘L’ is greater than or equal to one;
the CA bus is configured as an M-bit bus in which ‘M’ is greater than or equal to one; and
the at least one DQ bus is configured as an N-bit bus in which ‘N’ is greater than or equal to one.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising:
at least one memory controller (MC);
an interface operably coupled to the MC; and
wherein the first PHY and the second PHY are operably coupled to the interface.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the interface comprises a first interface and the apparatus further comprises:
at least one channel controller (CC);
a second interface operably coupled to the CC; and
wherein the at least one MC is operably coupled to the second interface.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein:
the at least two PHYs comprise N PHYs in which ‘N’ is greater than or equal to two;
the at least one memory die comprise N×N memory dies; and
a first N memory dies are operably coupled to the first PHY via the CA bus and the at least one DQ bus of the first PHY;
a second N memory dies are operably coupled to the second PHY via the CA bus and the at least one DQ bus of the second PHY;
a first memory die of the first N memory dies is operably coupled to the second PHY via the CS bus of the second PHY; and
a first memory die of the second N memory dies is operably coupled to the first PHY via the CS bus of the first PHY.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein:
the at least one DQ bus includes N DQ buses in which ‘N’ is greater than or equal to two; or
the N×N memory dies are packaged together in a stacked-die or linked-die architecture.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein:
the at least one memory die comprises at least one memory array;
the apparatus is configured as one of a Compute Express Link™ (CXL) memory module, a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or a small outline DIMM (SO-DIMM); or
the at least one memory die is one of a double data rate (DDR) die, DDR2 die, DDR3 die, DDR4 die, DDR5 die, DDR6 die, synchronous dynamic random-access memory (SDRAM) die, low-power DDR (LPDDR) SDRAM die, graphics DDR (GDDR) SDRAM die, or high-bandwidth memory (HBM) die.

### Claim 11

A method comprising:
receiving, by a memory die of multiple memory dies, a CS signal via a CS bus of a first PHY of multiple PHYs;
enabling, based on the CS signal, the memory die to receive commands and addresses; and
receiving, by the memory die, a CA signal via a CA bus of a second PHY of the multiple PHYs; and
characterizing, based on the CA signal, the CA bus of the second PHY of the multiple PHYs; or
receiving, by the memory die, a DQ signal via a DQ bus of the second PHY of the multiple PHYs; and
characterizing, based on the DQ signal, the DQ bus of the second PHY of the multiple PHYS.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the characterizing of the CA bus of the second PHY of the multiple PHYs comprises performing a CA bus training procedure; or
the characterizing of the DQ bus of the second PHY of the multiple PHYs comprises performing a DQ bus training procedure.

### Claim 13 (depends on 11)

The method of claim 11, wherein the memory die comprises a first memory die and the method further comprises:
receiving, by a second memory die of the multiple memory dies, a CS signal via a CS bus of the second PHY of the multiple PHYs;
enabling, based on the CS signal, the second memory die to receive commands and addresses; and
receiving, by the second memory die, a CA signal via a CA bus of the first PHY of the multiple PHYS.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
detecting, by the second memory die, the CA signal via the CA bus of the first PHY of the multiple PHYs as a no-operation command; and
performing, based on the detecting of the no-operation command, a no-operation; or
detecting, by the second memory die, the CA signal via the CA bus of the first PHY of the multiple PHYs as a deselect command; and
performing, based on the detecting of the deselect command, a deselect operation.

### Claim 15

An apparatus comprising:
a PHY comprising:
at least two CS buses comprising a first CS bus and a second CS bus;
at least two CA buses comprising a first CA bus and a second CA bus;
at least two DQ buses comprising a first DQ bus and a second DQ bus; and
at least two memory dies comprising a first memory die and a second memory die,
the first memory die operably coupled to the PHY via the first CS bus, the second CA bus, and the second DQ bus; and
the second memory die operably coupled to the PHY via the second CS bus, the first CA bus, and the first DQ bus.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein:
the at least two DQ buses comprise five DQ buses that include the first DQ bus, the second DQ bus, a third DQ bus, a fourth DQ bus, and a fifth DQ bus; and
the at least two memory dies comprise 20 memory dies.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein:
a first 10 memory dies of the 20 memory dies are operably coupled to the PHY via the first CA bus; and
a second 10 memory dies of the 20 memory dies are operably coupled to the PHY via the second CA bus.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein:
a first eight memory dies of the first 10 memory dies are operably coupled to the PHY via the first CS bus;
a remaining two memory dies of the first 10 memory dies are operably coupled to the PHY via the second CS bus;
a first eight memory dies of the second 10 memory dies are operably coupled to the PHY via the second CS bus; and
a remaining two memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the first CS bus.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein:
a first four memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the first DQ bus;
a second four memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the second DQ bus;
a remaining two memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the fifth DQ bus;
a first four memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the third DQ bus;
a second four memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the fourth DQ bus; and
a remaining two memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the fifth DQ bus.

### Claim 20 (depends on 15)

The apparatus of claim 15, wherein:
the at least two CS buses are L-bit buses in which ‘L’ is greater than or equal to one;
the at least two CA buses are M-bit buses in which ‘M’ is greater than or equal to one; and
the at least two DQ buses are N-bit buses in which ‘N’ is greater than or equal to one.