# US 2024/0202087 A1 · Routing raw debug data using trace infrastructure in processor-based devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0202087 A1 - Document ID: US20240202087A1 - Status: Published application - Kind: A1 - Application number: 18/498,583 - Filed: 2023-10-31 - Published: 2024-06-20 - Earliest claimed: 2022-12-19 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Sreeram Jayadev; Vinod Chamarty - Web page: https://patentgrep.com/patent/US20240202087A1 ## CPC - G06F 11/2221: {to test input/output devices or peripheral units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Routing raw debug data using trace infrastructure in processor-based devices is disclosed. In some aspects, a processor-based device comprises a trace interconnect bus, a subsystem circuit comprising a debug transmit circuit, and an input/output (I/O) endpoint circuit. The debug transmit circuit is configured to receive raw debug data from the subsystem circuit, and generate a debug trace packet comprising the raw debug data in lieu of formatted trace data. The debug transmit circuit is also configured to transmit the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity. In this manner, an existing trace infrastructure can be employed to transmit raw debug data without incurring expense in terms of overhead and monetary cost due to the need for industry-standard, infrastructure-compliant tools to decode conventionally packetized trace data for analysis. ## Claims ### Claim 1 A processor-based device, comprising: a trace interconnect bus; a subsystem circuit comprising a debug transmit circuit; and an input/output (I/O) endpoint circuit; the debug transmit circuit configured to: receive raw debug data from the subsystem circuit; generate a debug trace packet comprising the raw debug data in lieu of formatted trace data; and transmit the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity. ### Claim 2 (depends on 1) The processor-based device of claim 1, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus. ### Claim 3 (depends on 1) The processor-based device of claim 1, wherein the period of trace interconnect bus inactivity comprises a boot stage. ### Claim 4 (depends on 1) The processor-based device of claim 1, wherein the debug transmit circuit is further configured to: receive a debug enable signal; and responsive to receiving the debug enable signal, selectively enable debug functionality of the debug transmit circuit. ### Claim 5 (depends on 4) The processor-based device of claim 4, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits; and the debug transmit circuit is configured to selectively enable the debug functionality of the debug transmit circuit by being configured to selectively enable only the debug transmit circuit among the plurality of debug transmit circuits. ### Claim 6 (depends on 4) The processor-based device of claim 4, wherein the debug transmit circuit is further configured to transmit a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal. ### Claim 7 (depends on 1) The processor-based device of claim 1, wherein the I/O endpoint circuit comprises a debug receive circuit configured to: receive the debug trace packet comprising the raw debug data from the debug transmit circuit; extract the raw debug data from the debug trace packet; and transmit the raw debug data to a trace sink. ### Claim 8 (depends on 7) The processor-based device of claim 7, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins. ### Claim 9 (depends on 7) The processor-based device of claim 7, wherein: the debug receive circuit comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data; and the debug receive circuit is configured to extract the raw debug data and transmit the raw debug data to the trace sink based on the I/O configuration register. ### Claim 10 (depends on 1) The processor-based device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. ### Claim 11 A processor-based device, comprising: means for receiving raw debug data from a subsystem circuit of the processor-based device; means for generating a debug trace packet comprising the raw debug data in lieu of formatted trace data; and means for transmitting, via a trace interconnect bus of the processor-based device, the debug trace packet comprising the raw debug data to an I/O endpoint circuit of the processor-based device during a period of trace interconnect bus inactivity. ### Claim 12 A method for routing raw debug data using trace infrastructure, comprising: receiving, by a debug transmit circuit of a subsystem circuit of a processor-based device, raw debug data from the subsystem circuit; generating, by the debug transmit circuit, a debug trace packet comprising the raw debug data in lieu of formatted trace data; and transmitting, by the debug transmit circuit via a trace interconnect bus of the processor-based device, the debug trace packet comprising the raw debug data to an input/output (I/O) endpoint circuit of the processor-based device during a period of trace interconnect bus inactivity. ### Claim 13 (depends on 12) The method of claim 12, wherein the trace interconnect bus comprises an Advanced Microcontroller Bus Architecture (AMBA) trace bus (ATB) interconnect bus. ### Claim 14 (depends on 12) The method of claim 12, wherein the period of trace interconnect bus inactivity comprises a boot stage. ### Claim 15 (depends on 12) The method of claim 12, further comprising: receiving, by the debug transmit circuit, a debug enable signal; and responsive to receiving the debug enable signal, selectively enabling debug functionality of the debug transmit circuit. ### Claim 16 (depends on 15) The method of claim 15, wherein: the debug transmit circuit comprises one of a plurality of debug transmit circuits of a corresponding plurality of subsystem circuits of the processor-based device; and selectively enabling debug functionality of the debug transmit circuit comprises selectively enabling only the debug transmit circuit among the plurality of debug transmit circuits. ### Claim 17 (depends on 15) The method of claim 15, further comprising transmitting, by the debug transmit circuit, a training pattern to the I/O endpoint circuit, responsive to receiving the debug enable signal. ### Claim 18 (depends on 12) The method of claim 12, further comprising: receiving, by a debug receive circuit of the I/O endpoint circuit, the debug trace packet comprising the raw debug data from the debug transmit circuit; extracting, by the debug receive circuit, the raw debug data from the debug trace packet; and transmitting, by the debug receive circuit, the raw debug data to a trace sink. ### Claim 19 (depends on 18) The method of claim 18, wherein the trace sink comprises one or more of a system memory, an embedded trace buffer, a Trace Port Interface Unit (TPIU), and one or more General Purpose I/O (GPIO) pins. ### Claim 20 (depends on 18) The method of claim 18, wherein: the debug receive circuit comprises an I/O configuration register specifying one or more of a number of General Purpose I/O (GPIO) pins and an identification of one or more bits of the raw debug data; and extracting the raw debug data comprises extracting the raw debug data based on the I/O configuration register; and transmitting the raw debug data to the trace sink comprises transmitting the raw debug data based on the I/O configuration register.