# US 2024/0202070 A1 · Data storage device and method for performing error recovery > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0202070 A1 - Document ID: US20240202070A1 - Status: Published application - Kind: A1 - Application number: 18/219,087 - Filed: 2023-07-06 - Published: 2024-06-20 - Earliest claimed: 2022-12-16 - Assignees: Silicon Motion, Inc. - Applicants: Silicon Motion, Inc. - Inventors: Fu-Jen Shih - Web page: https://patentgrep.com/patent/US20240202070A1 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time. ## Claims ### Claim 1 A data storage device, comprising: an interface circuit, configured to process reception signals received from a peer device and transmission signals to be transmitted to the peer device, wherein the interface circuit comprises a signal processing circuit configured to perform an error recovery procedure when an error has occurred in the data storage device, and when performing the error recovery procedure, the signal processing circuit determines to perform an operation of line reset and determines which type of line reset is to be performed according to a device identifier, when the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device, and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time. ### Claim 2 (depends on 1) The data storage device of claim 1, wherein when determining that a first signal handshake procedure has failed, the signal processing circuit determines to perform the operation of line reset, and wherein the signal processing circuit tries to trigger the first signal handshake procedure by transmitting a first predetermined request signal to the peer device for at least one time. ### Claim 3 (depends on 2) The data storage device of claim 2, wherein the signal processing circuit requests to reset a current transmission rate in the first signal handshake procedure. ### Claim 4 (depends on 2) The data storage device of claim 2, wherein in the first signal handshake procedure, the signal processing circuit requests to maintain a current transmission rate at a predetermined transmission rate that is being used by the data storage device when the error occurred. ### Claim 5 (depends on 2) The data storage device of claim 2, wherein the first predetermined request signal is a power mode change request signal defined by the Mobile Industry Processor Interface (MIPI) alliance. ### Claim 6 (depends on 1) The data storage device of claim 1, wherein the signal processing circuit transmits the line reset signal to the peer device by setting voltages on a pair of differential signal transmission paths based on a specific pattern. ### Claim 7 (depends on 1) The data storage device of claim 1, wherein the data storage device is comprised in a data storage system, and the peer device is a host device accessing the data storage device in the data storage system. ### Claim 8 (depends on 1) The data storage device of claim 1, wherein in the operation of periodic line reset, when the signal processing circuit has not received any line reset signal from the peer device when the predetermined period expires, the signal processing circuit determines that error recovery has failed, and when the signal processing circuit has received said another line reset signal from the peer device before the predetermined period expires, the signal processing circuit further transmits a second predetermined request signal to trigger a second signal handshake procedure. ### Claim 9 (depends on 8) The data storage device of claim 8, wherein when determining that the second signal handshake procedure has failed, the signal processing circuit determines that the error recovery has failed, and when determining that the second signal handshake procedure is successful, the signal processing circuit determines that the error recovery is successful. ### Claim 10 (depends on 8) The data storage device of claim 8, wherein the signal processing circuit sets a current transmission rate to a lowest transmission rate to transmit the second predetermined request signal, and requests to restore the current transmission rate to a predetermined transmission rate that is being used by the data storage device when the error occurred in the second signal handshake procedure. ### Claim 11 A method for performing error recovery, applied in an error recovery procedure performed by a signal processing circuit when an error has occurred in a data storage device, comprising: transmitting a first predetermined request signal to a peer device to try to trigger a first signal handshake procedure; determining which type of line reset is to be performed according to a device identifier when determining that the first signal handshake procedure has failed; performing an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device when the device identifier satisfies a predetermined condition; and performing an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time when the device identifier does not satisfy the predetermined condition. ### Claim 12 (depends on 11) The method of claim 11, further comprising: requesting to reset a current transmission rate in the first signal handshake procedure. ### Claim 13 (depends on 11) The method of claim 11, further comprising: requesting to maintain a current transmission rate at a predetermined transmission rate that is being used by the data storage device when the error occurred in the first signal handshake procedure. ### Claim 14 (depends on 11) The method of claim 11, wherein the first predetermined request signal is a power mode change request signal defined by the Mobile Industry Processor Interface (MIPI) alliance. ### Claim 15 (depends on 11) The method of claim 11, wherein the line reset signal is transmitted by setting voltages on a pair of differential signal transmission paths based on a specific pattern. ### Claim 16 (depends on 11) The method of claim 11, wherein the signal processing circuit is comprised in an interface circuit of the data storage device. ### Claim 17 (depends on 11) The method of claim 11, wherein when performing the operation of periodic line reset, the method further comprises: determining that the error recovery has failed when the line reset signal is determined to have not been received by the peer device, wherein when the signal processing circuit has not received any line reset signal from the peer device when the predetermined period expires, the line reset signal is determined to have not been received by the peer device; and transmitting a second predetermined request signal to trigger a second signal handshake procedure when the line reset signal is determined to have been received by the peer device. ### Claim 18 (depends on 17) The method of claim 17, further comprising: determining that the error recovery has failed when the second signal handshake procedure is determined to have failed; and determining that the error recovery is successful when the second signal handshake procedure is determined successful. ### Claim 19 (depends on 17) The method of claim 17, wherein the second predetermined request signal is transmitted at a current transmission rate which is set to a lowest transmission rate, and in the second signal handshake procedure, the current transmission rate is requested to be restored to a predetermined transmission rate that is being used by the data storage device when the error occurred.