# US 2024/0202069 A1 · Memory controller and memory system including the same

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- Number: US 2024/0202069 A1
- Document ID: US20240202069A1
- Status: Published application
- Kind: A1
- Application number: 18/376,637
- Filed: 2023-10-04
- Published: 2024-06-20
- Earliest claimed: 2022-12-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyung Jin PARK; Sung-Joon Kim; Ho-Young Lee; Kyung-Hee Han
- Web page: https://patentgrep.com/patent/US20240202069A1

## CPC

- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 2029/0409: {Online test}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system, a memory controller are provided. The memory system includes: a memory device; and a memory controller configured to: control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; and adaptively adjust the scrubbing cycle based on a comparison of an error count value of the memory device and a plurality of risk threshold values.

## Claims

### Claim 1

A memory system comprising:
a memory device; and
a memory controller configured to:
control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; and
adaptively adjust the scrubbing cycle based on a comparison of an error count value of the memory device and a plurality of risk threshold values.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the error count value indicates a number of correctable errors that have occurred in the memory device.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the memory controller is further configured to::
increase the error count value based on a correctable error being detected by the patrol scrubbing operation;
identify an address of a memory cell in which the correctable error has been detected; and
updated fail information based on the error count value and the address.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the memory controller is further configured to control the patrol scrubbing operation to be performed for memory cells adjacent to the stored address.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the plurality of risk threshold values are stored as register bits for a memory access operation.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the memory controller further configured to set the scrubbing cycle to:
a first scrubbing cycle based on the error count value being less than a first risk threshold value; and
a second scrubbing cycle shorter than the first scrubbing cycle based on the error count value being equal to or greater than the first risk threshold value and less than or equal to a second risk threshold value.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to, based on the memory device being in an active state, control the patrol scrubbing operation to be performed at the scrubbing cycle.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the memory controller is further configured to, based on the memory device being in an idle state, perform the patrol scrubbing operation at a preset idle scrubbing cycle.

### Claim 9

A memory system comprising:
a plurality of memory devices; and
a memory controller configured to identify a risk level based on fail information of the plurality of memory devices, set a scrubbing cycle in accordance with the risk level and control a patrol scrubbing operation to be performed at the scrubbing cycle.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the memory controller is further configured to control the patrol scrubbing operation to be performed the scrubbing cycle or an idle scrubbing cycle based on an operation state of the plurality of memory devices.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the memory controller is further configured to perform the patrol scrubbing operation at least two times within a set time period based on the plurality of memory devices being in an idle state.

### Claim 12 (depends on 9)

The memory system of claim 9, wherein the memory controller is further configured to:
read data from each of the plurality of memory devices;
increase an error count value based on a correctable error being detected in the data read from the plurality of memory devices; and
update the fail information based on the error count value and an address of a memory cell corresponding to the correctable error.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein the memory controller is further configured to:
determine the risk level based on a comparison of the error count value and a plurality of risk thresholds; and
set the scrubbing cycle based on the risk level.

### Claim 14 (depends on 13)

The memory system of claim 13, wherein the memory controller is further configured to:
set the scrubbing cycle to a first scrubbing cycle based on the error count value being less than a first risk threshold value; and
set the scrubbing cycle to a second scrubbing cycle shorter than the first scrubbing cycle based on the error count value being equal to or greater than the first risk threshold value and less than or equal to a second risk threshold value.

### Claim 15 (depends on 12)

The memory system of claim 12, wherein the memory controller is further configured to control the patrol scrubbing operation for a memory chip corresponding to the address at the scrubbing cycle.

### Claim 16

A memory controller comprising:
a non-volatile memory storing fail information; and
a processor configured to control:
a scrubbing cycle to be set based on the fail information; and
an Error Correction Code (ECC) engine to perform a scrubbing operation in which a bit error of data read from a memory device is detected and corrected, and corrected data is written in the memory device, at the scrubbing cycle.

### Claim 17 (depends on 16)

The memory controller of claim 16, wherein the processor is further configured to:
increase an error count value based on the bit error being detected; and
update the fail information based on the error count value.

### Claim 18 (depends on 17)

The memory controller of claim 17, wherein the processor is further configured to:
determine a risk level from among a plurality of risk levels based on a comparison of the error count value and a plurality of risk threshold values; and
set the scrubbing cycle corresponding to the risk level.

### Claim 19 (depends on 18)

The memory controller of claim 18, wherein information of the plurality of risk threshold values, the plurality of risk levels and a plurality of scrubbing cycles corresponding to the plurality of risk levels is stored as register bits.

### Claim 20 (depends on 17)

The memory controller of claim 17, wherein the fail information indicates an address of a memory cell in which the bit error is detected.

### Claim 21

(canceled)