# US 2024/0202047 A1 · Systems and methods for chiplet synchronization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0202047 A1 - Document ID: US20240202047A1 - Status: Published application - Kind: A1 - Application number: 18/082,882 - Filed: 2022-12-16 - Published: 2024-06-20 - Earliest claimed: 2022-12-16 - Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC - Applicants: Advanced Micro Devices, Inc.; ATI Technologies ULC - Inventors: Joseph L. Greathouse; Alan D. Smith; Anthony Asaro; Kostantinos Danny Christidis; Alexander Fuad Ashkar; Milind N. Nemlekar - Web page: https://patentgrep.com/patent/US20240202047A1 ## CPC - G06F 9/522: {Barrier synchronisation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed. ## Claims ### Claim 1 A computer-implemented method, at least a portion of the method being performed by a computing device comprising a plurality of chiplets, the method comprising: reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier; receiving, by the chiplet, dedicated control messages that are pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets; and advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. ### Claim 2 (depends on 1) The method of claim 1, wherein the control network corresponds to an on-chip network that provides connections between the chiplet and at least one of the other chiplets. ### Claim 3 (depends on 2) The method of claim 2, wherein the connections are point-to-point connections. ### Claim 4 (depends on 2) The method of claim 2, wherein the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connections between the chiplet and at least one of the other chiplets. ### Claim 5 (depends on 1) The method of claim 1, wherein the chiplet and at least one of the other chiplets are implemented on different chips. ### Claim 6 (depends on 1) The method of claim 1, further comprising: pushing, by the chiplet and in response to reaching the synchronization barrier, one or more outgoing dedicated control messages, wherein the one or more outgoing dedicated control messages are pushed to the other chiplets over the control network. ### Claim 7 (depends on 1) The method of claim 1, further comprising: maintaining, by the chiplet, a set of counters that includes at least one counter for each of the other chiplets. ### Claim 8 (depends on 7) The method of claim 7, further comprising: incrementing counters of the set of counters in response to receipt of the dedicated control messages. ### Claim 9 (depends on 1) The method of claim 1, wherein advancing the synchronization barrier further occurs in response to reaching the synchronization barrier. ### Claim 10 A system comprising: a chiplet processor; and physical memory comprising computer-executable instructions that, when executed by the chiplet processor in carrying out an operation for a process, cause the chiplet processor to: reach, by a chiplet involved in carrying out an operation for a process, a synchronization barrier; receive, by the chiplet, dedicated control messages that are pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets; and advance, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. ### Claim 11 (depends on 10) The system of claim 10, wherein the control network corresponds to an on-chip network that provides connections between the chiplet and at least one of the other chiplets. ### Claim 12 (depends on 11) The system of claim 11, wherein the connections are point-to-point connections. ### Claim 13 (depends on 11) The system of claim 11, wherein the control network corresponds to a separate control network implemented in parallel with a separate data network that also provides connections between the chiplet and at least one of the other chiplets. ### Claim 14 (depends on 10) The system of claim 10, wherein the chiplet and at least one of the other chiplets are implemented on different chips. ### Claim 15 (depends on 10) The system of claim 10, wherein the instructions further cause the chiplet processor to: push, in response to reaching the synchronization barrier, one or more outgoing dedicated control messages, wherein the one or more outgoing dedicated control messages are pushed to the other chiplets over the control network. ### Claim 16 (depends on 10) The system of claim 10, wherein the instructions further cause the chiplet processor to: maintain a set of counters that includes at least one counter for each of the other chiplets. ### Claim 17 (depends on 16) The system of claim 16, wherein the instructions further cause the chiplet processor to: increment counters of the set of counters in response to receipt of the dedicated control messages. ### Claim 18 (depends on 10) The system of claim 10, wherein advancing the synchronization barrier further occurs in response to reaching the synchronization barrier. ### Claim 19 A non-transitory computer-readable medium comprising one or more computer-executable instructions that, when executed by a chiplet processor carrying out an operation for a process, cause the chiplet processor to: reach, by a chiplet involved in carrying out an operation for a process, a synchronization barrier; receive, by the chiplet, dedicated control messages that are pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets; and advance, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, wherein the control network corresponds to an on-chip network that provides connections between the chiplet and at least one of the other chiplets.