# US 2024/0202033 A1 · Accelerator control system, accelerator control method and accelerator control program

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- Number: US 2024/0202033 A1
- Document ID: US20240202033A1
- Status: Published application
- Kind: A1
- Application number: 18/287,192
- Filed: 2021-04-22
- Published: 2024-06-20
- Earliest claimed: 2021-04-22
- Assignees: Nippon Telegraph and Telephone Corporation
- Applicants: Nippon Telegraph and Telephone Corporation
- Inventors: Tomoya YOKONO; Yoshiro YAMABE; Teruaki ISHIZAKI
- Web page: https://patentgrep.com/patent/US20240202033A1

## CPC

- G06F 9/3881: {Arrangements for communication of instructions and data}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)}
- G06F 15/167: using a common memory, e.g. mailbox
- G06F 13/1673: {using buffers}
- G06F 2209/509: Offload
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An accelerator control system includes an accelerator control device and a plurality of accelerators, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and each of the accelerators includes second processing circuitry configured to acquire the control data from the storage, and perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing of the accelerator included in the acquired control data.

## Claims

### Claim 1

An accelerator control system comprising an accelerator control device and a plurality of accelerators,
wherein the accelerator control device includes:
first processing circuitry configured to:
store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator; and
determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and
each of the accelerators includes:
second processing circuitry configured to:
acquire the control data from the storage;
perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing of the accelerator included in the acquired control data;
store the control data in the storage when the arithmetic processing is completed and the control data does not include information on a transfer destination accelerator;
transfer the control data to the transfer destination accelerator when the control data includes information on the transfer destination accelerator; and
arithmetic unit configured to perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing included in the control data when the control data has been received from another accelerator.

### Claim 2 (depends on 1)

The accelerator control system according to claim 1, wherein the second processing circuitry is further configured to check whether or not the control data is receivable from another accelerator.

### Claim 3 (depends on 2)

The accelerator control system according to claim 2, wherein the second processing circuitry is further configured to retransmit the control data when the transfer destination accelerator does not notify of whether or not the control data is receivable within a predetermined time.

### Claim 4 (depends on 1)

The accelerator control system according to claim 1, wherein the second processing circuitry is further configured to:
store a result of the arithmetic processing performed on the data which is an arithmetic processing target in the storage when the control data has been transferred to the transfer destination accelerator, and
read the result of the arithmetic processing stored in the storage and set the result of the arithmetic processing as the arithmetic processing target.

### Claim 5 (depends on 1)

The accelerator control system according to claim 1, wherein the second processing circuitry is further configured to monitor whether or not the control data is present in the storage.

### Claim 6 (depends on 1)

The accelerator control system according to claim 1, wherein the first processing circuitry is further configured to monitor whether or not the control data which has been subjected to arithmetic processing is present in the storage.

### Claim 7

An accelerator control method executed by an accelerator control system including an accelerator control device and a plurality of accelerators,
wherein the accelerator control system includes a storage configured to store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator,
the accelerator control method comprising:
acquiring the control data from the storage;
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;
storing the control data in the storage when the arithmetic processing is completed and the control data does not include information on a transfer destination accelerator;
determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored in the storage,
transferring the control data to the transfer destination accelerator when the control data includes information on the transfer destination accelerator; and
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing included in the control data when the control data has been received from another accelerator.

### Claim 8

A non-transitory computer-readable recording medium storing therein an accelerator control program that causes a computer to execute a process comprising:
acquiring the control data from a storage configured to store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator;
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;
storing the control data in the storage when the arithmetic processing is completed and the control data does not include information on a transfer destination accelerator;
determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored in the storage,
transferring the control data to the transfer destination accelerator when the control data includes information on the transfer destination accelerator; and
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing included in the control data when the control data has been received from another accelerator.