# US 2024/0202000 A1 · Device, method and system to capture or restore microarchitectural state of a processor core > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0202000 A1 - Document ID: US20240202000A1 - Status: Published application - Kind: A1 - Application number: 18/084,425 - Filed: 2022-12-19 - Published: 2024-06-20 - Earliest claimed: 2022-12-19 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Niranjan Soundararajan; Sreenivas Subramoney - Web page: https://patentgrep.com/patent/US20240202000A1 ## CPC - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques and mechanisms for efficiently saving and recovering state of a processor core. In an embodiment, a processor core fetches and decodes a first instruction to generate a first decoded instruction, wherein the first instruction comprises a first opcode which corresponds to one or more components of the processor core. Execution of the first instruction comprises saving microarchitectural state of the one or more components to a memory of the core. In another embodiment, a processor core fetches and decodes a second instruction to generate a second decoded instruction, wherein the second instruction comprises a second opcode which corresponds to the same one or more components. Execution of the second instruction comprises restoring the microarchitectural state from the memory to the one or more components. ## Claims ### Claim 1 A processor core comprising: fetch circuitry to fetch a first instruction comprising a first opcode which is to correspond to a first one or more components of the processor core; a decoder circuit coupled to the fetch circuitry, the decoder to decode the first instruction to generate a first decoded instruction; and an execution circuit coupled to receive the first decoded instruction, wherein the execution circuit is to execute the first decoded instruction to save a microarchitectural state of the first one or more components to a repository of the processor core. ### Claim 2 (depends on 1) The processor core of claim 1, further comprising a branch prediction unit (BPU), wherein the first one or more components is the BPU. ### Claim 3 (depends on 1) The processor core of claim 1, further comprising a branch target buffer (BTB), wherein the first one or more components is the BTB. ### Claim 4 (depends on 1) The processor core of claim 1, further comprising a micro-operation cache, wherein the first one or more components is the micro-operation cache. ### Claim 5 (depends on 1) The processor core of claim 1, further comprising: a branch prediction unit (BPU); a branch target buffer (BTB); and a micro-operation cache; wherein the first one or more components comprises two or more of the BPU, the BTB, or the micro-operation cache. ### Claim 6 (depends on 1) The processor core of claim 1, wherein: the fetch circuitry is further to fetch a second instruction comprising a second opcode which is to correspond to the first one or more components; the decoder is further to decode the second instruction to generate a second decoded instruction; and the execution circuit is further to execute the second decoded instruction to restore the microarchitectural state from the repository to the first one or more components. ### Claim 7 (depends on 6) The processor core of claim 6, wherein the microarchitectural state is a first microarchitectural state, and wherein: the fetch circuitry is further to fetch a third instruction comprising a third opcode which is to correspond to a second one or more components of the processor core; the decoder is further to decode the third instruction to generate a third decoded instruction; and the execution circuit is further to execute the third decoded instruction to save a second microarchitectural state of the second one or more components to the repository. ### Claim 8 (depends on 7) The processor core of claim 7, wherein: the fetch circuitry is further to fetch a fourth instruction comprising a fourth opcode which is to correspond to the second one or more components; the decoder is further to decode the fourth instruction to generate a fourth decoded instruction; and the execution circuit is further to execute the fourth decoded instruction to restore the second microarchitectural state from the repository to the second one or more components. ### Claim 9 (depends on 1) The processor core of claim 1, wherein the microarchitectural state is a first microarchitectural state, and wherein: the fetch circuitry is further to fetch a second instruction comprising a second opcode which is to correspond to a second one or more components of the processor core; the decoder is further to decode the second instruction to generate a second decoded instruction; and the execution circuit is further to execute the second decoded instruction to save a second microarchitectural state of the second one or more components to the repository. ### Claim 10 A method at a processor core, the method comprising: fetching a first instruction comprising a first opcode which is to correspond to a first one or more components of the processor core; decoding the first instruction to generate a first decoded instruction; and executing the first decoded instruction, comprising saving a microarchitectural state of the first one or more components to a repository of the processor core. ### Claim 11 (depends on 10) The method of claim 10, wherein the first one or more components is a branch prediction unit (BPU) of the processor core. ### Claim 12 (depends on 10) The method of claim 10, wherein the first one or more components is a branch target buffer (BTB) of the processor core. ### Claim 13 (depends on 10) The method of claim 10, wherein the first one or more components is a micro-operation cache of the processor core. ### Claim 14 (depends on 10) The method of claim 10, further comprising: fetching a second instruction comprising a second opcode which is to correspond to the first one or more components; decoding the second instruction to generate a second decoded instruction; and executing the second decoded instruction to restore the microarchitectural state from the repository to the first one or more components. ### Claim 15 A system comprising: a memory to store a plurality of instructions; a processor core coupled to the memory, the processor core comprising: fetch circuitry to fetch a first instruction of the plurality of instructions, the first instruction comprising a first opcode which is to correspond to a first one or more components of the processor core; a decoder circuit coupled to the fetch circuitry, the decoder to decode the first instruction to generate a first decoded instruction; and an execution circuit coupled to receive the first decoded instruction, wherein the execution circuit is to execute the first decoded instruction to save a microarchitectural state of the first one or more components to a repository of the processor core. ### Claim 16 (depends on 15) The system of claim 15, the processor core further comprising a branch prediction unit (BPU), wherein the first one or more components is the BPU. ### Claim 17 (depends on 15) The system of claim 15, the processor core further comprising a branch target buffer (BTB), wherein the first one or more components is the BTB. ### Claim 18 (depends on 15) The system of claim 15, the processor core further comprising a micro-operation cache, wherein the first one or more components is the micro-operation cache. ### Claim 19 (depends on 15) The system of claim 15, the processor core further comprising: a branch prediction unit (BPU); a branch target buffer (BTB); and a micro-operation cache; wherein the first one or more components comprises two or more of the BPU, the BTB, or the micro-operation cache. ### Claim 20 (depends on 15) The system of claim 15, wherein: the fetch circuitry is further to fetch a second instruction comprising a second opcode which is to correspond to the first one or more components; the decoder is further to decode the second instruction to generate a second decoded instruction; and the execution circuit is further to execute the second decoded instruction to restore the microarchitectural state from the repository to the first one or more components.