# US 2024/0201991 A1 · Vector reverse

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2024/0201991 A1
- Document ID: US20240201991A1
- Status: Published application
- Kind: A1
- Application number: 18/404,238
- Filed: 2024-01-04
- Published: 2024-06-20
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Timothy D. Anderson; Duc Bui
- Web page: https://patentgrep.com/patent/US20240201991A1

## CPC

- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30038: {using a mask}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30105: {Register structure}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Processors and methods reverse source data in response to a vector reverse instruction. In an implementation, a processor comprises an instruction fetch unit; and a datapath that includes a register file that includes a source register and a destination register; and a set of functional units. The instruction fetch unit receives a vector reverse instruction that specifies a single vector reverse operation to be executed in a single operation. The vector reverse instruction also specifies a first functional unit from among a set of functional units, and based on the vector reverse instruction, the first functional unit receives the first vector from a source register; reverses an order of a set of elements of a first vector stored in the source register to produce a second vector; and causes the second vector to be stored in a destination register.

## Claims

### Claim 1

A processor comprising:
an instruction fetch unit configured to receive a vector reverse instruction that specifies a single vector reverse operation; and
a datapath coupled to the instruction fetch unit that includes:
a register file that includes a source register configured to store a first vector that includes a set of elements and a destination register; and
a set of functional units coupled to the register file that includes a first functional unit, wherein:
the vector reverse instruction specifies the first functional unit from among the set of functional units; and
the first functional unit is configured to, based on the vector reverse instruction:
receive the first vector from the source register;
reverse an order of the set of elements of the first vector to produce a second vector; and
cause the second vector to be stored in the destination register,
wherein the vector reverse instruction is executed in a single operation.

### Claim 2 (depends on 1)

The processor of claim 1, wherein:
the instruction fetch unit is configured to receive a second instruction; and
the vector reverse instruction specifies whether the processor is permitted to execute the vector reverse instruction and the second instruction in parallel.

### Claim 3 (depends on 1)

The processor of claim 1, wherein:
the datapath is a first datapath;
the processor further comprises a second datapath; and
the vector reverse instruction specifies the first datapath to perform the vector reverse instruction.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the vector reverse instruction specifies a size of each element of the set of elements.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the vector reverse instruction specifies the size of each element of the set of elements from among a byte, a half-word, a word, and a double word.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the vector reverse instruction specifies the source register and the destination register within the register file.

### Claim 7 (depends on 1)

The processor of claim 1, further comprising an instruction decoder coupled between the instruction fetch unit and the datapath and configured to cause the first functional unit to receive the first vector, reverse the order of the set of elements to produce the second vector, and store the second vector.

### Claim 8 (depends on 1)

The processor of claim 1, further comprising:
a processor core that includes the instruction fetch unit and the datapath;
a level one cache coupled to the processor core;
a level two cache coupled to the level one cache; and
a streaming engine coupled between the level two cache and the processor core in parallel with the level one cache, wherein the streaming engine is configured to retrieve the first vector from the level two cache and provide the first vector to the processor core for storing in the source register.

### Claim 9

A processor comprising:
an instruction fetch unit configured to receive a vector reverse instruction and a second instruction, wherein the vector reverse instruction specifies whether the processor is to perform the vector reverse instruction and the second instruction in parallel and further specifies that the vector reverse instruction is a single vector reverse operation;
a register file that includes a source register configured to store a first vector that includes a set of elements and a destination register;
a functional unit coupled to the register file and configured to, based on the vector reverse instruction:
receive the first vector from the source register;
reverse an order of the set of elements of the first vector to produce a second vector; and
cause the second vector to be stored in the destination register, wherein the vector reverse instruction is completed in a single operation.

### Claim 10 (depends on 9)

The processor of claim 9, further comprising a set of functional units coupled to the register file that includes the functional unit, wherein the vector reverse instruction specifies the functional unit from among the set of functional units.

### Claim 11 (depends on 9)

The processor of claim 9, further comprising:
a first datapath that includes the register file and the functional unit; and
a second datapath, wherein the vector reverse instruction specifies the first datapath.

### Claim 12 (depends on 9)

The processor of claim 9, wherein the vector reverse instruction specifies a size of each element of the set of elements.

### Claim 13 (depends on 12)

The processor of claim 12, wherein the vector reverse instruction specifies the size of each element of the set of elements from among a byte, a half-word, a word, and a double word.

### Claim 14 (depends on 9)

The processor of claim 9, wherein the vector reverse instruction specifies the source register and the destination register within the register file.

### Claim 15 (depends on 9)

The processor of claim 9, further comprising:
a processor core that includes the instruction fetch unit, the register file, and the functional unit;
a level one cache coupled to the processor core;
a level two cache coupled to the level one cache; and
a streaming engine coupled between the level two cache and the processor core in parallel with the level one cache, wherein the streaming engine is configured to retrieve the first vector from the level two cache and provide the first vector to the processor core for storing in the source register.

### Claim 16

A method comprising:
receiving a vector reverse instruction that specifies a source register from among a register file, a destination register from among the register file, and a functional unit from among a set of functional units, wherein the vector reverse instruction further specifies that the vector reverse instruction is single vector reverse operation; and
based on the vector reverse instruction, performing, by the specified functional unit:
receiving a first vector from the source register, wherein the first vector includes a set of elements;
reversing the set of elements of the first vector to produce a second vector; and
storing the second vector in the destination register,
wherein the vector reverse instruction is completed in a single operation.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
receiving a second instruction, wherein the vector reverse instruction specifies whether to perform the vector reverse instruction and the second instruction in parallel; and
determining whether to perform the vector reverse instruction and the second instruction in parallel based on the vector reverse instruction.

### Claim 18 (depends on 16)

The method of claim 16, wherein the vector reverse instruction specifies a datapath that includes the functional unit.

### Claim 19 (depends on 18)

The method of claim 18, wherein the datapath further includes the register file.

### Claim 20 (depends on 16)

The method of claim 16, wherein the vector reverse instruction specifies a size of each element of the set of elements.