# US 2024/0201986 A1 · Accelerator control system, accelerator control method and accelerator control program

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2024/0201986 A1
- Document ID: US20240201986A1
- Status: Published application
- Kind: A1
- Application number: 18/287,193
- Filed: 2021-04-22
- Published: 2024-06-20
- Earliest claimed: 2021-04-22
- Assignees: Nippon Telegraph and Telephone Corporation
- Applicants: Nippon Telegraph and Telephone Corporation
- Inventors: Tomoya YOKONO; Yoshiro YAMABE; Teruaki ISHIZAKI
- Web page: https://patentgrep.com/patent/US20240201986A1

## CPC

- G06F 9/28: Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 2209/509: Offload
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An accelerator control system includes an accelerator control device and an accelerator, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and the accelerator includes second processing circuitry configured to acquire the control data from the storage, perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator included in the acquired control data, and store the control data in the storage when the arithmetic processing is completed.

## Claims

### Claim 1

An accelerator control system comprising an accelerator control device and an accelerator,
wherein the accelerator control device includes:
first processing circuitry configured to:
store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator; and
determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and
the accelerator includes:
second processing circuitry configured to:
acquire the control data from the storage;
perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data; and
store the control data in the storage when the arithmetic processing is completed.

### Claim 2 (depends on 1)

The accelerator control system according to claim 1, wherein the second processing circuitry is further configured to monitor whether or not the control data is present in the storage.

### Claim 3 (depends on 1)

The accelerator control system according to claim 1, wherein the first processing circuitry is further configured to monitor whether or not the control data which has been subjected to the arithmetic processing is present in the storage.

### Claim 4 (depends on 1)

The accelerator control system according to claim 1, wherein the second processing circuitry is further configured to store, in the storage, a result of the arithmetic processing performed on the data which is an arithmetic processing target.

### Claim 5 (depends on 1)

The accelerator control system according to claim 1, wherein the first processing circuitry is further configured to store control data different for each of a plurality of accelerators.

### Claim 6

An accelerator control method executed by an accelerator control system including an accelerator control device and an accelerator,
wherein the accelerator control system includes a storage configured to store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator,
the accelerator control method comprising:
acquiring the control data from the storage;
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;
storing the control data in the storage when the arithmetic processing is completed; and
determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored in the storage.

### Claim 7

A non-transitory computer-readable recording medium storing therein an accelerator control program that causes a computer to execute a process comprising:
acquiring the control data from a storage configured to store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator;
performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;
storing the control data in the storage when the arithmetic processing is completed; and
determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored in the storage.