# US 2024/0201902 A1 · Method and non-transitory computer-readable storage medium and apparatus for executing host write commands > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201902 A1 - Document ID: US20240201902A1 - Status: Published application - Kind: A1 - Application number: 18/383,239 - Filed: 2023-10-24 - Published: 2024-06-20 - Earliest claimed: 2022-12-14 - Assignees: Silicon Motion, Inc. - Applicants: Silicon Motion, Inc. - Inventors: Shen-Ting CHIU - Web page: https://patentgrep.com/patent/US20240201902A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0625: {Power saving in storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; reading user data of the first logical address range from a first address of the RAM and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into the flash module. ## Claims ### Claim 1 A method for executing host write commands, performed by a processing unit, comprising: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue, wherein the SCQ stores a plurality of sequential write commands, the RCQ stores a plurality of random write commands, the mark queue comprises a record indicating that a conflicting sequential write command and/or a conflicting random write command needs to be processed in advance; when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; reading user data of the first logical address range from a first address of a random access memory (RAM) and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into a flash module. ### Claim 2 (depends on 1) The method of claim 1, wherein the specific condition is met during a time period between receptions of a first instruction and a second instruction from a host side, where the first instruction instructs to enter a sleep mode or a power saving mode, and the second instruction instructs to leave the sleep mode or the power saving mode. ### Claim 3 (depends on 1) The method of claim 1, wherein the specific condition is met when a total number of occupied nodes in the SCQ, the RCQ or the mark queue exceeds a threshold. ### Claim 4 (depends on 1) The method of claim 1, wherein the sequential write commands are queued in the SCQ in order from first to last based on reception times of the sequential write commands from a host side, and the random write commands are queued in the RCQ in order from first to last based on reception times of the random write commands from the host side. ### Claim 5 (depends on 1) The method of claim 1, wherein a length of a fifth logical address range carried in any sequential write command is greater than a threshold and a length of a sixth logical address range carried in any random write command is equal to or lower than the threshold. ### Claim 6 (depends on 5) The method of claim 5, wherein the threshold is set to 1. ### Claim 7 A non-transitory computer-readable storage medium having stored therein program code that, when loaded and executed by a processing unit, causes the processing unit to. provide a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue, wherein the SCQ stores a plurality of sequential write commands, the RCQ stores a plurality of random write commands, the mark queue comprises a record indicating that a conflicting sequential write command and/or a conflicting random write command needs to be processed in advance; when a specific condition is met, obtain a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; read user data of the first logical address range from a first address of a random access memory (RAM) and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and program the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into a flash module. ### Claim 8 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the specific condition is met during a time period between receptions of a first instruction and a second instruction from a host side, where the first instruction instructs to enter a sleep mode or a power saving mode, and the second instruction instructs to leave the sleep mode or the power saving mode. ### Claim 9 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the specific condition is met when a total number of occupied nodes in the SCQ, the RCQ or the mark queue exceeds a threshold. ### Claim 10 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the sequential write commands are queued in the SCQ in order from first to last based on reception times of the sequential write commands from a host side, and the random write commands are queued in the RCQ in order from first to last based on reception times of the random write commands from the host side. ### Claim 11 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein a length of a fifth logical address range carried in any sequential write command is greater than a threshold and a length of a sixth logical address range carried in any random write command is equal to or lower than the threshold. ### Claim 12 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein the threshold is set to 1. ### Claim 13 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the first address or the second address of the RAM is stored in the SCQ with each sequential write command, and the third address or the fourth address of the RAM is stored in the RCQ with each random write command. ### Claim 14 An apparatus for executing host write commands, comprising: a flash interface (I/F), coupled to a flash module; a random access memory (RAM), arranged operably to: allocate space for a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue, wherein the SCQ stores a plurality of sequential write commands, the RCQ stores a plurality of random write commands and the mark queue comprises a record indicating that a conflicting sequential write command and/or a conflicting random write command needs to be processed in advance; and a processing unit, coupled to the RAM and the flash I/F, arranged operably to: when a specific condition is met, obtain a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; read user data of the first logical address range from a first address of the RAM and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and drive the flash I/F to program the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into the flash module. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the specific condition is met during a time period between receptions of a first instruction and a second instruction from a host side, where the first instruction instructs to enter a sleep mode or a power saving mode, and the second instruction instructs to leave the sleep mode or the power saving mode. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the specific condition is met when a total number of occupied nodes in the SCQ, the RCQ or the mark queue exceeds a threshold. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein the sequential write commands are queued in the SCQ in order from first to last based on reception times of the sequential write commands from a host side, and the random write commands are queued in the RCQ in order from first to last based on reception times of the random write commands from the host side. ### Claim 18 (depends on 14) The apparatus of claim 14, wherein a length of a fifth logical address range carried in any sequential write command is greater than a threshold and a length of a sixth logical address range carried in any random write command is equal to or lower than the threshold. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the threshold is set to 1. ### Claim 20 (depends on 14) The apparatus of claim 14, wherein the first address or the second address of the RAM is stored in the SCQ with each sequential write command, and the third address or the fourth address of the RAM is stored in the RCQ with each random write command.