# US 2024/0201900 A1 · Memory device and storage device including the same

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- Number: US 2024/0201900 A1
- Document ID: US20240201900A1
- Status: Published application
- Kind: A1
- Application number: 18/311,893
- Filed: 2023-05-04
- Published: 2024-06-20
- Earliest claimed: 2022-12-16
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Byoung Sung YOU
- Web page: https://patentgrep.com/patent/US20240201900A1

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0626: {Reducing size or complexity of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device includes a cell region, a buffer region, and a control circuit configured to: sequentially store read commands in a queue, and control the cell region and the buffer region to perform grouped read operations of outputting respective data blocks requested by the respective read commands.

## Claims

### Claim 1

A memory device comprising:
a cell region;
a buffer region; and
a control circuit configured to:
sequentially store read commands in a queue, and
control the cell region and the buffer region to perform grouped read operations of outputting respective data blocks requested by the respective read commands.

### Claim 2 (depends on 1)

The memory device according to claim 1,
wherein the grouped read operations comprise sequential internal read operations on the respective data blocks and sequential output operations on the respective data blocks, and
wherein the internal read operations partially overlap the output operations.

### Claim 3 (depends on 2)

The memory device according to claim 2,
wherein each of the internal read operations comprises reading a corresponding data block from the cell region to buffer the read data block into the buffer region, and
wherein each of the output operations comprises outputting the buffered data block from the buffer region to an outside.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the grouped read operations comprise:
performing a first output operation after completing a first internal read operation on a first data block among the data blocks; and
performing a second internal read operation on a second data block among the data blocks in parallel with the first output operation.

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein the grouped read operations further comprise performing a second output operation on the second data block after completing the second internal read operation and the first output operation.

### Claim 6 (depends on 5)

The memory device according to claim 5,
wherein the first output operation comprises a first cache transfer operation and a first cache output operation, and
wherein the control circuit is further configured to:
output a ready/busy signal at a logic low level while performing the first internal read operation and the first cache transfer operation,
change a level of the ready/busy signal to a logic high level after completing the first cache transfer operation, and
output the ready/busy signal at the logic high level while performing the first cache output operation.

### Claim 7 (depends on 6)

The memory device according to claim 6,
wherein the second output operation comprises a second cache transfer operation and a second cache output operation, and
wherein the control circuit is further configured to:
change the level of the ready/busy signal to the logic low level after completing the second internal read operation, and
output the ready/busy signal at the logic low level while performing the second cache transfer operation.

### Claim 8 (depends on 7)

The memory device according to claim 7, wherein the control circuit is further configured to:
change the level of the ready/busy signal to the logic high level after completing the second cache transfer operation, and
output the ready/busy signal at the logic high level while performing the second cache output operation.

### Claim 9 (depends on 1)

The memory device according to claim 1, wherein the control circuit comprises an operation command manager configured to:
select, as an index, either a variable index or a fixed index according to a result of comparing a reference size with a data size of a corresponding read command, and
allocate the selected index to the read command when storing the read command in the queue.

### Claim 10 (depends on 9)

The memory device according to claim 9, wherein the operation command manager selects the variable index when the data size is equal to or less than the reference size and selects the fixed index when the data size exceeds the reference size.

### Claim 11 (depends on 9)

The memory device according to claim 9, wherein the control circuit is further configured to:
receive the read commands to be stored in the queue, and
set a queue depth of the queue and the reference size in response to a set command before receiving the read commands.

### Claim 12 (depends on 1)

The memory device according to claim 1, wherein the control circuit is further configured to:
receive a first read command among the read commands,
output a ready/busy signal at a logic low level while storing the first read command in the queue, and
change a level of the ready/busy signal to a logic high level to receive a second read command subsequent to the first read command after storing the first read command in the queue.

### Claim 13

A memory device comprising:
a cell region; and
a control circuit configured to:
set a queue depth and a reference size in response to a set command,
compare a data size of a read command with the reference size when storing the read command in a queue, and
allocate an index to the read command according to a result of the comparison.

### Claim 14 (depends on 13)

The memory device according to claim 13, wherein the reference size is a capacity of a page included in the cell region.

### Claim 15 (depends on 13)

The memory device according to claim 13,
wherein the control circuit allocates a variable index to the read command when the data size is equal to or less than the reference size, and allocates a fixed index to the read command when the data size exceeds the reference size, and
wherein the variable index varies in a range corresponding to the queue depth.

### Claim 16

A storage device comprising:
a memory device; and
a controller configured to:
sequentially transmit read commands to the memory device, and
sequentially receive data blocks respectively corresponding to the read commands from the memory device.

### Claim 17 (depends on 16)

The storage device according to claim 16,
wherein the memory device is configured to:
receive the read commands,
sequentially perform internal read operations on the respective data blocks, and
sequentially perform output operations on the respective data blocks, and
wherein the internal read operations partially overlap the output operations.

### Claim 18 (depends on 16)

The storage device according to claim 16,
wherein the controller is further configured to select the read commands satisfying a predetermined condition, and
wherein the predetermined condition is that target memory regions of the read commands are included in substantially the same plane in the memory device and a data size of each of the read commands is equal to or less than a reference size.

### Claim 19 (depends on 16)

The storage device according to claim 16,
wherein the controller is further configured to transmit a set command to the memory device before transmitting the read commands, and
wherein the memory device is configured to set, in response to the set command, a queue depth of a queue in which the read commands are to be stored.

### Claim 20 (depends on 16)

The storage device according to claim 16,
wherein the controller transmits a first read command among the read commands to the memory device when a ready/busy signal outputted from the memory device has a logic high level, and
wherein the memory device is configured to:
output, after receiving the first read command, the ready/busy signal at a logic low level while storing the first read command in a queue, and
change a level of the ready/busy signal to a logic high level in order to receive a second read command subsequent to the first read command after storing the first read command in the queue.