# US 2024/0201888 A1 · Opportunistic storage of non-write-boosted data in write booster cache memory

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- Number: US 2024/0201888 A1
- Document ID: US20240201888A1
- Status: Published application
- Kind: A1
- Application number: 18/505,661
- Filed: 2023-11-09
- Published: 2024-06-20
- Earliest claimed: 2022-12-15
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Giuseppe CARIELLO; Jonathan S. PARRY; Reshmi BASU
- Web page: https://patentgrep.com/patent/US20240201888A1

## CPC

- G06F 3/065: {Replication mechanisms}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

## Claims

### Claim 1

A memory device, comprising:
a non-volatile cache memory; and
one or more controllers configured to:
receive, from a host device, an indication of a threshold amount of the non-volatile cache memory to be reserved for first data for which write boosting is activated;
receive, from the host device, a write command that includes second data for which write boosting is deactivated;
determine that the second data is hot data;
identify a block of the non-volatile cache memory using a write boost cursor based on determining that the second data is hot data, based on the indication of the threshold amount, and despite write boosting being deactivated for the second data; and
write the second data to the block of the non-volatile cache memory.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the one or more controllers, to identify the block using the write boost cursor, are configured to:
identify the block using the write boost cursor based on a determination that writing the second data to the non-volatile cache memory will not reduce an available amount of non-volatile cache memory reserved for the first data below the threshold amount.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the one or more controllers are further configured to copy hot data stored in the block to a first new block and copy cold data stored in the block to a second new block during a garbage collection operation performed on the block.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the first new block is a first block of non-volatile main memory and the second new block is a second block of the non-volatile main memory.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the first new block is a new block of the non-volatile cache memory and the second new block is a new block of non-volatile main memory.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein the one or more controllers are configured to copy the hot data to the first new block and copy the cold data to the second new block during the garbage collection operation based on one or more block age parameters associated with the non-volatile cache memory.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the indication of the threshold amount comprises a threshold size or a threshold percentage.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising storing small fragment data, having a size less than a page line size of a page line of the memory device, in the block of the non-volatile cache memory.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein a portion of the non-volatile cache memory is reserved for the small fragment data.

### Claim 10

A method, comprising:
receiving, by a memory device, a write command that includes data to be written to the memory device;
receiving, by the memory device, an indication that single-level cell data caching is deactivated for the data;
determining, by the memory device, whether the data is associated with a first data type or a second data type; and
selectively writing, by the memory device, the data to single-level cell cache memory or multi-level cell main memory based on:
a determination of whether the data is associated with the first data type or the second data type, and
a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first data type is associated with an expected lifespan that is shorter than an expected lifespan associated with the second data type.

### Claim 12 (depends on 10)

The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the single-level cell cache memory based on:
a determination that the data is associated with the first data type, and
a determination that the single-level cell cache memory has sufficient memory, that is not reserved for the single-level cell data caching, to store the data.

### Claim 13 (depends on 10)

The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the multi-level cell main memory based on a determination that the data is associated with the second data type.

### Claim 14 (depends on 10)

The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the multi-level cell main memory based on a determination that the single-level cell cache memory does not have sufficient memory, that is not reserved for the single-level cell data caching, to store the data.

### Claim 15 (depends on 10)

The method of claim 10, further comprising receiving, from a host device, an indication of an amount of memory in the single-level cell cache memory to be reserved for the single-level cell data caching, and
wherein the determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching is based on the amount of memory in the single-level cell cache memory to be reserved for the single-level cell data caching.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
identifying a block of the single-level cell cache memory for which a garbage collection operation is to be performed;
identifying a first set of pages, included in the block, that store first data associated with the first data type;
identifying a second set of pages, included in the block, that store second data associated with the second data type;
copying the first data to a first block as part of performing the garbage collection operation; and
copying the second data to a second block as part of performing the garbage collection operation.

### Claim 17 (depends on 16)

The method of claim 16, wherein both the first block and the second block are included in the multi-level cell main memory, or
wherein the first block is included in the single-level cell cache memory and the second block is included in the multi-level cell main memory.

### Claim 18

An apparatus, comprising:
a non-volatile memory array; and
a controller configured to execute instructions that cause the apparatus to:
process a received command to write data to the non-volatile memory array, wherein the command is received without an indication that the data is to be written in a single-level cell (SLC) cache memory of the non-volatile memory array;
determine whether the data is associated with a first data type;
determine whether the SLC cache memory has sufficient memory not reserved for SLC data caching; and
write the data to the SLC cache memory based on a determination that the data is associated with the first data type and that the SLC cache memory has sufficient memory not reserved for SLC data caching.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the controller is configured to executed instructions that cause the apparatus to:
write the data to a multi-level cell memory of the non-volatile memory array based on a determination that the data is not associated with the first data type or that the SLC cache memory does not have sufficient memory not reserved for SLC data caching.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the first data type is expected to become invalid or is expected to be overwritten in a shorter amount of time than a second data type.