# US 2024/0201882 A1 · Temperature compensation for pre-charge spike in multi-pass programming > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201882 A1 - Document ID: US20240201882A1 - Status: Published application - Kind: A1 - Application number: 18/220,707 - Filed: 2023-07-11 - Published: 2024-06-20 - Earliest claimed: 2022-12-20 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Jiacen Guo; Xiang Yang - Web page: https://patentgrep.com/patent/US20240201882A1 ## CPC - G06F 3/064: {Management of blocks} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation. ## Claims ### Claim 1 A method of programming a memory device, comprising the steps of: preparing a memory block that includes a plurality of memory cells arranged in a plurality of word lines; determining an operating temperature of the memory device; selecting a spike pre-charge voltage based on the operating temperature of the memory device; programming a first word line and a second word line in a first programming pass of a multi-pass programming operation; and after the first programming pass is completed on the first and second word lines, further programming the first word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the second word line during each pre-charge operation. ### Claim 2 (depends on 1) The method as set forth in claim 1, further comprising the step of comparing the operating temperature of the memory device to a threshold temperature. ### Claim 3 (depends on 2) The method as set forth in claim 2, wherein the step of selecting the spike pre-charge voltage includes selecting a first spike pre-charge voltage in response to the operating temperature of the memory device being greater than the threshold temperature and includes selecting a second spike pre-charge voltage in response to the operating temperature of the memory device being less than the threshold temperature. ### Claim 4 (depends on 3) The method as set forth in claim 3, wherein the second spike pre-charge voltage is greater than the first spike pre-charge voltage. ### Claim 5 (depends on 4) The method as set forth in claim 4, wherein a difference between the second spike pre-charge voltage and the first spike pre-charge voltage is determined by a difference between the operating temperature of the memory device and the threshold temperature. ### Claim 6 (depends on 1) The method as set forth in claim 1, further including the steps of: programming a third word line in a first programming pass; and after the first programming pass is completed on the third word line, further programming the second word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the third word line during each pre-charge operation. ### Claim 7 (depends on 1) The method as set forth in claim 1, wherein during the pre-charge operations of the second programming pass, a non-spike pre-charge voltage is applied to at least one of the plurality of word lines in the memory block, and wherein the non-spike pre-charge voltage is less than the spike pre-charge voltage. ### Claim 8 (depends on 1) The method as set forth in claim 1, wherein during the first programming pass, the memory cells of the one of the plurality of word lines being programmed are programmed to less than a final number of programmed data states and wherein during the second programming pass, the memory cells of the one of the plurality of word lines being programmed are programmed to the final number of programmed data states. ### Claim 9 (depends on 1) The method as set forth in claim 1, wherein during the first programming pass, the memory cells of the one of the plurality of word lines being programmed are programmed to a final number of programmed data states and wherein during the second programming pass, the memory cells of the one of the plurality of word lines being programmed are further programmed to the same final number of programmed data states. ### Claim 10 A memory device, comprising: a memory block that includes a plurality of memory cells arranged in a plurality of word lines; control circuitry in electrical communication with the plurality of memory cells, the control circuitry being configured to: determine an operating temperature of the memory device; select a spike pre-charge voltage based on the operating temperature of the memory device; program a first word line and a second word line in a first programming pass of a multi-pass programming operation; and after the first programming pass is completed on the first and second word lines, further program the first word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the second word line by the control circuitry during each pre-charge operation. ### Claim 11 (depends on 10) The memory device as set forth in claim 10, wherein the control circuitry is further configured to compare the operating temperature of the memory device to a threshold temperature. ### Claim 12 (depends on 11) The memory device as set forth in claim 11, wherein the control circuitry is further configured to select a first spike pre-charge voltage in response to the operating temperature of the memory device being greater than the threshold temperature and select a second spike pre-charge voltage in response to the operating temperature of the memory device being less than the threshold temperature. ### Claim 13 (depends on 12) The memory device as set forth in claim 12, wherein the second spike pre-charge voltage is greater than the first spike pre-charge voltage. ### Claim 14 (depends on 13) The memory device as set forth in claim 13, wherein a difference between the second spike pre-charge voltage and the first spike pre-charge voltage is determined by a difference between the operating temperature of the memory device and the threshold temperature. ### Claim 15 (depends on 10) The memory device as set forth in claim 10, wherein the control circuitry is further configured to: program a third word line in a first programming pass; and after the first programming pass is completed on the third word line, further program the second word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the third word line during each pre-charge operation. ### Claim 16 (depends on 10) The memory device as set forth in claim 10, wherein during the pre-charge operations of the second programming pass, the control circuitry applies a non-spike pre-charge voltage to at least one of the plurality of word lines in the memory block, and wherein the non-spike pre-charge voltage is less than the spike pre-charge voltage. ### Claim 17 (depends on 10) The memory device as set forth in claim 10, wherein during the first programming pass, the control circuitry programs the memory cells of the one of the plurality of word lines being programmed to less than a final number of programmed data states and wherein during the second programming pass, the control circuitry programs the memory cells of the one of the plurality of word lines being programmed to the final number of programmed data states. ### Claim 18 (depends on 10) The memory device as set forth in claim 10, wherein during the first programming pass, the control circuitry programs the memory cells of the one of the plurality of word lines being programmed to a final number of programmed data states and wherein during the second programming pass, the control circuitry programs the memory cells of the one of the plurality of word lines being programmed to the same final number of programmed data states. ### Claim 19 An apparatus, comprising: a memory block that includes a plurality of memory cells arranged in a plurality of word lines; a programming means for programming the memory cells to a plurality of data states such that each memory cell retains a plurality of bits of data, the programming means being in electrical communication with the plurality of memory cells, and the programming means being configured to: determine an operating temperature of the memory device; compare the operating temperature of the memory device to a threshold temperature; set a spike pre-charge voltage as a high temperature spike pre-charge voltage in response to the operating temperature of the memory device being above the threshold temperature and as a low temperature spike pre-charge voltage in response to the operating temperature of the memory device being below the threshold temperature, the low temperature spike pre-charge voltage being greater than the high temperature spike pre-charge voltage; program a first word line and a second word line in a first programming pass of a multi-pass programming operation; and after the first programming pass is completed on the first and second word lines, further program the first word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the second word line by the control circuitry during each pre-charge operation. ### Claim 20 (depends on 19) The apparatus as set forth in claim 19, wherein the programming means is further configured to: program a third word line in a first programming pass; and after the first programming pass is completed on the third word line, further program the second word line in a second programming pass that includes a plurality of program loops with pre-charge operations, and wherein the spike pre-charge voltage is applied to the third word line during each pre-charge operation.