# US 2024/0201878 A1 · Row address latching for multiple activate command protocol > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201878 A1 - Document ID: US20240201878A1 - Status: Published application - Kind: A1 - Application number: 18/593,620 - Filed: 2024-03-01 - Published: 2024-06-20 - Earliest claimed: 2022-08-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kwang-Ho Cho; Miki Matsumoto - Web page: https://patentgrep.com/patent/US20240201878A1 ## CPC - G06F 3/0625: {Power saving in storage systems} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G11C 8/04: using a sequential addressing device, e.g. shift register, counter - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 11/2253: {Address circuits or decoders} - G11C 11/2293: {Timing circuits or methods} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits. ## Claims ### Claim 1 A method, comprising: receiving a first activate command that indicates first values for a first set of bits of a row address; receiving a second activate command that indicates first values for a second set of bits of the row address; receiving a third activate command indicating second values for the first set of bits of the row address; and activating a page of memory using the first values for the first set of bits and the first values for the second set of bits, wherein activating the page is performed based at least in part on receiving the second activate command, and occurs after receiving the third activate command. ### Claim 2 (depends on 1) The method of claim 1, further comprising: receiving a fourth activate command that indicates first values for a third set of bits of the row address, wherein receiving the fourth activate command occurs after receiving the first activate command and prior to receiving the second activate command. ### Claim 3 (depends on 2) The method of claim 2, wherein: each bit of the first set of bits is more significant than each bit of the second set of bits, and each bit of the second set of bits is more significant than each bit of the third set of bits. ### Claim 4 (depends on 1) The method of claim 1, further comprising: receiving a fourth activate command that indicates second values for the second set of bits of the row address; and activating a second page of memory using the second values for the first set of bits and the second values for the second set of bits, wherein activating the second page is performed based at least in part on receiving the fourth activate command and occurs after activating the page. ### Claim 5 (depends on 4) The method of claim 4, further comprising: receiving a fifth activate command that indicates third values for the first set of bits, wherein the fifth activate command is received prior to activating the second page of memory. ### Claim 6 (depends on 1) The method of claim 1, wherein the second activate command indicates a selected bank for the page of memory. ### Claim 7 (depends on 1) The method of claim 1, wherein a time duration between the second activate command and the third activate command is shorter than a row to row delay time. ### Claim 8 (depends on 1) The method of claim 1, wherein a time duration between the second activate command and the third activate command is shorter than a clock cycle. ### Claim 9 A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: receive a first activate command that indicates first values for a first set of bits of a row address; receive a second activate command that indicates first values for a second set of bits of the row address; receive a third activate command indicating second values for the first set of bits of the row address; and activate a page of memory using the first values for the first set of bits and the first values for the second set of bits, wherein the activation of the page is performed based at least in part on reception of the second activate command, and occurs after reception of the third activate command. ### Claim 10 (depends on 9) The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the one or more processors to: receive a fourth activate command that indicates first values for a third set of bits of the row address, wherein reception of the fourth activate command occurs after reception of the first activate command and prior to reception of the second activate command. ### Claim 11 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein: each bit of the first set of bits is more significant than each bit of the second set of bits, and each bit of the second set of bits is more significant than each bit of the third set of bits. ### Claim 12 (depends on 9) The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the one or more processors to: receive a fourth activate command that indicates second values for the second set of bits of the row address; and activate a second page of memory using the second values for the first set of bits and the second values for the second set of bits, wherein activation of the second page is performed based at least in part on reception of the fourth activate command and occurs after activation of the page. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the one or more processors to: receive a fifth activate command that indicates third values for the first set of bits, wherein the fifth activate command is received prior to activation of the second page of memory. ### Claim 14 (depends on 9) The non-transitory computer-readable medium of claim 9, wherein the second activate command indicates a selected bank for the page of memory. ### Claim 15 (depends on 9) The non-transitory computer-readable medium of claim 9, wherein a time duration between the second activate command and the third activate command is shorter than a row to row delay time. ### Claim 16 An apparatus, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and operable to execute the code to cause the apparatus to: receive a first activate command that indicates first values for a first set of bits of a row address; receive a second activate command that indicates first values for a second set of bits of the row address; receive a third activate command indicating second values for the first set of bits of the row address; and activate a page of memory using the first values for the first set of bits and the first values for the second set of bits, wherein activating the page occurs after receiving the third activate command. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the apparatus to: receive a fourth activate command that indicates first values for a third set of bits of the row address, wherein reception of the fourth activate command occurs after reception of the first activate command and prior to reception of the second activate command. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein: each bit of the first set of bits is more significant than each bit of the second set of bits, and each bit of the second set of bits is more significant than each bit of the third set of bits. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the apparatus to: receive a fourth activate command that indicates second values for the second set of bits of the row address; and activate a second page of memory using the second values for the first set of bits and the second values for the second set of bits, wherein activating the second page is performed based at least in part on reception of the fourth activate command and occurs after activating the page. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the one or more processors are individually or collectively further operable to execute the code to cause the apparatus to: receive a fifth activate command that indicates third values for the first set of bits, wherein the fifth activate command is received prior to activating the second page of memory.