# US 2024/0201877 A1 · System with mcu and flash memory and control method for deep power down control thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201877 A1 - Document ID: US20240201877A1 - Status: Published application - Kind: A1 - Application number: 18/209,638 - Filed: 2023-06-14 - Published: 2024-06-20 - Earliest claimed: 2022-12-19 - Assignees: Gigadevice Semiconductor Inc. - Applicants: Gigadevice Semiconductor Inc. - Inventors: Yang GAO - Web page: https://patentgrep.com/patent/US20240201877A1 ## CPC - G06F 1/3225: of memory devices - G06F 3/0625: {Power saving in storage systems} - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/30: Power supply circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract The present invention provides a system with an MCU and flash memory and a method for DPD control thereof. A new DPD mode (first DPD mode) is provided by simply adding a power supply pin to the MCU. The power supply pin is coupled to a power supply terminal of the flash memory. In a deep power down mode, the flash memory is configured to be entirely powered down, leading to even lower system power consumption than in a conventional DPD mode (second DPD mode). ## Claims ### Claim 1 A system with a microcontroller unit (MCU) and a flash memory, wherein the flash memory is configured to store codes and/or data for the MCU and comprises a first circuit portion and a second circuit portion, and wherein the MCU comprises at least one power supply pin coupled to a power supply terminal of the flash memory, wherein, in a normal mode, the MCU is configured to utilize a power supply control signal to enable power to be supplied to the power supply terminal of the flash memory, thereby allowing a normal operation of each of the first and second circuit portions; and in a first deep power down (DPD) mode, the MCU is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory, thereby powering down each of the first and second circuit portions. ### Claim 2 (depends on 1) The system of claim 1, wherein in a second DPD mode, the MCU is configured to utilize the power supply control signal to enable power to be supplied to the power supply terminal of the flash memory, thereby allowing a normal operation of the first circuit portion while powering down the second circuit portion, and/or wherein the first circuit portion comprises a circuitry configured to restore the flash memory from the second DPD mode to the normal mode. ### Claim 3 (depends on 2) The system of claim 2, further comprising a power supply switching module, wherein an input terminal of the power supply switching module is coupled to a power supply required for the flash memory; an output terminal of the power supply switching module is coupled to the power supply pin; and a control terminal of the power supply switching module is coupled to the power supply control signal, wherein in the normal mode and the second DPD mode, the MCU is configured to utilize the power supply control signal to maintain the power supply switching module turned on, enabling the power supply to supply power to the flash memory, and wherein in the first DPD mode, the MCU is configured to utilize the power supply control signal to turn off the power supply switching module. ### Claim 4 (depends on 3) The system of claim 3, wherein the power supply switching module comprises an analog switch circuit, wherein an input terminal of the analog switch circuit is coupled to the power supply; an output terminal of the analog switch circuit is coupled to the power supply pin; and a control terminal of the analog switch circuit is coupled to the power supply control signal. ### Claim 5 (depends on 4) The system of claim 4, wherein the power supply switching module further comprises a voltage conversion circuit, wherein an input terminal of the voltage conversion circuit is coupled to the output terminal of the analog switch circuit; and an output terminal of voltage conversion circuit is coupled to the power supply pin. ### Claim 6 (depends on 3) The system of claim 3, wherein the power supply switching module is arranged outside the MCU; or the power supply switching module is integrated in a circuit of an analog domain of the MCU. ### Claim 7 (depends on 2) The system of claim 2, wherein the MCU further comprises: a flash memory controller communicatively connected to the flash memory through a communication bus interface, wherein the flash memory controller is configured to send, through the communication bus interface, instructions for control of read, write and erase operations performed on the flash memory and instructions for control of operating modes, and to detect a status of the flash memory when receiving a DPD mode signal; and a power management unit coupled to each of the flash memory controller and the power supply control signal, wherein when receiving the DPD mode signal, the power management unit is configured to utilize the power supply control signal to maintain or cut off power supplied to the power supply terminal of the flash memory, based on the DPD mode signal and the status detected by the flash memory controller. ### Claim 8 (depends on 7) The system of claim 7, wherein a DPD mode control bit is configured in the MCU, and wherein, when the DPD mode signal is not received by the power management unit, the system operates in the normal mode in which the power management unit is configured to utilize the power supply control signal to maintain power supplied to the power supply terminal of the flash memory; when the DPD mode signal is received by the power management unit and the DPD mode control bit is unset, the power management unit is configured to utilize the power supply control signal to maintain power supplied to the power supply terminal of the flash memory, the flash memory controller sends a DPD mode instruction to the flash memory, and the flash memory enters the second DPD mode in response to the DPD mode instruction; and when the DPD mode signal is received by the power management unit and the DPD mode control bit is set, the power management unit is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory, enabling the system to enter the first DPD mode. ### Claim 9 (depends on 8) The system of claim 8, wherein when the DPD mode signal is received by the power management unit and the DPD mode control bit is set, in case of detecting the flash memory being idle by the flash memory controller, the power management unit is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory. ### Claim 10 (depends on 8) The system of claim 8, wherein the DPD mode control bit is configured in a configuration register in the power management unit. ### Claim 11 (depends on 7) The system of claim 7, wherein the MCU further comprises a processing core, wherein in case of receiving a deep sleep instruction, the processing core sends the DPD mode signal to each of the flash memory controller and the power management unit. ### Claim 12 (depends on 7) The system of claim 7, wherein the MCU further comprises an unauthorized access monitoring module coupled to the power management unit, wherein in case of detecting an unauthorized external access, the unauthorized access monitoring module is configured to output an access signal to the power management unit, and based on the access signal, the power management unit is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory. ### Claim 13 (depends on 12) The system of claim 12, wherein an access control bit is further configured in the MCU, and wherein when the power management unit receives the access signal and the access control bit is set, the power management unit is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory. ### Claim 14 (depends on 13) The system of claim 13, wherein the access control bit is configured in a configuration register in the power management unit. ### Claim 15 (depends on 1) The system of claim 1, wherein the MCU and the flash memory are integrated in a single package using a system-in-package (SIP) technique. ### Claim 16 A method for deep power down (DPD) control of a system with a microcontroller unit (MCU) and a flash memory, wherein the flash memory is configured to store codes and/or data for the MCU and comprises a first circuit portion and a second circuit portion; the MCU comprises at least one power supply pin coupled to a power supply terminal of the flash memory; and the method comprises: when entry of the system into a deep sleep mode is required, the MCU is configured to utilize a power supply control signal to cut off power to the power supply terminal of the flash memory, enabling the flash memory to enter a first DPD mode in which each of the first and second circuit portions is powered down. ### Claim 17 (depends on 16) The method of claim 16, wherein when entry of the system into the deep sleep mode is required and a DPD mode control bit in the MCU is set, the MCU detects whether the flash memory is idle, and wherein in case of detecting of the flash memory being idle, the MCU is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory. ### Claim 18 (depends on 16) The method of claim 16, further comprising: when entry of the system into the deep sleep mode is required and a DPD mode control bit in the MCU is unset, maintaining power supplied to the power supply terminal of the flash memory and sending a DPD mode instruction from the MCU to the flash memory, wherein the flash memory enters a second DPD mode in response to the DPD mode instruction, in which the first circuit portion of the flash memory remains in operation while the second circuit portion of the flash memory is powered down. ### Claim 19 (depends on 18) The method of claim 18, wherein after the flash memory enters the first DPD mode or the second DPD mode, associated circuits of the MCU are powered down, enabling the system to enter the deep sleep mode. ### Claim 20 (depends on 17) The method of claim 17, wherein the DPD mode control bit is configured in a configuration register in a power management unit of the MCU.