# US 2024/0201871 A1 · Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2024/0201871 A1
- Document ID: US20240201871A1
- Status: Published application
- Kind: A1
- Application number: 18/428,157
- Filed: 2024-01-31
- Published: 2024-06-20
- Earliest claimed: 2020-12-01
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: JEREMY CHRITZ; DAVID HULTON
- Web page: https://patentgrep.com/patent/US20240201871A1

## CPC

- G06F 3/0622: {in relation to access}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0638: {Organizing or formatting or addressing of data}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0877: Cache access modes
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}
- H04L 9/065: {Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3}
- G06F 2212/60: Details of cache memory
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- H04L 2209/34: Encoding or coding, e.g. Huffman coding or error correction
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

## Claims

### Claim 1

An apparatus comprising:
a memory controller comprising:
authentication logic circuitry configured to utilize a received memory address as an initialization vector for an authenticated stream cipher to generate an access code; and
translation logic circuitry configured to perform address translation using the received memory address and a command associated with the received memory address to translate a logical address of the received memory address to a physical memory address, wherein the translation logic circuitry is configured to perform the address translation, at least in part, in parallel with generation of the access code.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory controller further comprises:
error correction circuitry configured to generate an error correction code for data associated with the command, wherein the error correction circuitry is configured to generate the error correction code, at least in part, in parallel with the generation of the access code.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the error correction circuitry includes a single error correction, double error detection algorithm error correction code unit circuit configured to generate the error correction code.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the error correction circuitry includes a low-density parity-check correction algorithm unit configured to generate the error correction code.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising:
a cache configured to store data associated with the received memory address; and
a memory configured to perform an access operation associated with the command using the access code, the data, and the physical memory address.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the memory comprises a NAND memory device.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the memory controller is configured to receive the command and the memory address from a host computing device via a PCIe bus.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the authentication logic circuitry includes an Advance Encryption Standard Galois/Counter Mode (AES-GCM) pipeline for generating the access code.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the authentication logic circuitry is configured to use the access code to encrypt data as ciphertext.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the translation logic circuitry is configured to perform at least one of memory wear leveling, garbage collection, or write amplification.

### Claim 11

A method comprising:
receiving, from a host computing device, an access command and a memory address; and
responsive to the access command:
generating an access code, wherein generating the access code includes using the memory address as an initialization vector for an authenticated stream cipher to generate the access code; and
performing address translation using the memory address and the access command to translate a logical address to a physical address, wherein the address translation is performed, at least in part, in parallel with generation of the access code.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing an access operation associated with the access command using the access code and the physical address.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
generating error correction code for data associated with the access command, wherein the error correction code is generated, at least in part, in parallel with the generation of the access code.

### Claim 14 (depends on 13)

The method of claim 13, wherein the error correction code is generated at least in part using a single error correction, double error detection algorithm error correction code unit circuit.

### Claim 15 (depends on 13)

The method of claim 13, wherein the error correction code is generated at least in part using a low-density parity-check correction algorithm unit.

### Claim 16 (depends on 11)

The method of claim 11, wherein the access command and the memory address are received from the host computing device at a cache of a memory controller via a host bus.

### Claim 17 (depends on 11)

The method of claim 11, wherein the authenticated stream cipher comprises an advanced encryption standard (AES) cipher.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
generating, at a Galois/Counter Mode (GCM) of an authentication logic circuit, the access code based on the AES cipher.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
performing a XOR-operation to combine the access code and data associated with the access command to be written to a memory device.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
encrypting the data as ciphertext data; and
generating an authentication tag associated with the ciphertext data.