# US 2024/0201860 A1 · Address mappings for random access operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201860 A1 - Document ID: US20240201860A1 - Status: Published application - Kind: A1 - Application number: 18/511,814 - Filed: 2023-11-16 - Published: 2024-06-20 - Earliest claimed: 2022-12-16 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Wenjun Wu; Huachen Li; Xiaolai Zhu; Ling Shi; Qingyuan Wang - Web page: https://patentgrep.com/patent/US20240201860A1 ## CPC - G06F 3/0613: {in relation to throughput} - G06F 3/061: {Improving I/O performance} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 2212/1016: Performance improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for address mappings for random access operations are described. A portion of a L2P table may be loaded (e.g., to a buffer) upon receiving a write command (e.g., a random write command). In some instances, one or more entries (e.g., one or more mappings) included in the portion of the L2P table may be updated based on the write command. The portion of the L2P table may be maintained in the buffer during subsequent access operations, such as random read operations. The subsequent access operations may utilize the portion of the L2P table to access a memory device. ## Claims ### Claim 1 An apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: receive a write command comprising a logical address associated with one or more non-volatile memory cells; update, at a buffer of the memory device, a mapping between the logical address and a physical address of the one or more non-volatile memory cells based at least in part on receiving the write command; transfer information stored in the buffer to the one or more non-volatile memory cells based at least in part on updating the information in the buffer; receive a read command comprising the logical address based at least in part on updating the mapping between the logical address and the physical address of the one or more non-volatile memory cells; and read, using the updated mapping stored in the buffer of the memory device, the physical address of the one or more non-volatile memory cells corresponding to the logical address based at least in part on receiving the read command. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: maintain the updated mapping in the buffer of the memory device for a duration, wherein reading the physical address of the one or more non-volatile memory cells corresponding to the logical address occurs during the duration. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: transmit an indication of the updated mapping from the buffer of the memory device to the one or more non-volatile memory cells during the duration. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: load the mapping to the buffer of the memory device based at least in part on receiving the write command, wherein updating the mapping between the logical address and the physical address is based at least in part on loading the mapping to the buffer. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a second write command comprising a plurality of logical addresses associated with the memory device; update, at the buffer of the memory device, mappings between each logical address of the plurality of logical addresses and a corresponding physical address of the one or more non-volatile memory cells based at least in part on receiving the second write command; receive a second read command comprising a subset of the plurality of logical addresses based at least in part on updating the mappings between each logical address of the plurality of logical addresses and a corresponding physical address of the one or more non-volatile memory cells; and read, using the updated mappings at the buffer of the memory device, physical addresses of the one or more non-volatile memory cells corresponding to the subset of the plurality of logical addresses based at least in part on receiving the second read command. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: maintain the updated mappings between each logical address of the plurality of logical addresses and the corresponding physical address of the one or more non-volatile memory cells in the buffer of the memory device for a second duration, wherein reading the physical addresses of the one or more non-volatile memory cells corresponding to the subset of the plurality of logical addresses occurs during the second duration. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: write data to the physical address of the one or more non-volatile memory cells based at least in part on receiving the write command. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the write command comprises a random write command, and wherein the read command comprises a random read command. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: update a change-log of changes to the mapping based at least in part on receiving the write command, wherein updating the mapping is based at least in part on updating the change-log. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the controller is further configured to cause the apparatus to: transfer a portion of the mapping from the one or more non-volatile memory cells to the buffer based at least in part on updating the change-log, wherein updating the mapping is based at least in part on transferring the portion of the mapping and on one or more entries in the change-log. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the buffer comprises a mapping merge buffer. ### Claim 12 A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: receive a write command comprising a logical address associated with a memory system comprising non-volatile memory cells; update, at a buffer of the memory system, a mapping between the logical address and a physical address of the non-volatile memory cells based at least in part on receiving the write command; transfer information stored in the buffer to the non-volatile memory cells based at least in part on updating the information in the buffer; receive a read command comprising the logical address based at least in part on updating the mapping between the logical address and the physical address of the non-volatile memory cells; and read, using the updated mapping stored in the buffer of the memory system, the physical address of the non-volatile memory cells corresponding to the logical address based at least in part on receiving the read command. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: maintain the updated mapping in the buffer of the memory system for a duration, wherein reading the physical address of the non-volatile memory cells corresponding to the logical address occurs during the duration. ### Claim 14 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: transmit an indication of the updated mapping from the buffer of the memory system to the non-volatile memory cells during the duration. ### Claim 15 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: load the mapping to the buffer of the memory system based at least in part on receiving the write command, wherein updating the mapping between the logical address and the physical address is based at least in part on loading the mapping to the buffer. ### Claim 16 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive a second write command comprising a plurality of logical addresses associated with the memory system; update, at the buffer of the memory system, mappings between each logical address of the plurality of logical addresses and a corresponding physical address of the non-volatile memory cells based at least in part on receiving the second write command; receive a second read command comprising a subset of the plurality of logical addresses based at least in part on updating the mappings between each logical address of the plurality of logical addresses and a corresponding physical address of the non-volatile memory cells; and read, using the updated mappings at the buffer of the memory system, physical addresses of the non-volatile memory cells corresponding to the subset of the plurality of logical addresses based at least in part on receiving the second read command. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: maintain the updated mappings between each logical address of the plurality of logical addresses and the corresponding physical address of the non-volatile memory cells in the buffer of the memory system for a second duration, wherein reading the physical addresses of the non-volatile memory cells corresponding to the subset of the plurality of logical addresses occurs during the second duration. ### Claim 18 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: write data to the physical address of the non-volatile memory cells based at least in part on receiving the write command. ### Claim 19 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the write command comprises a random write command, and wherein the read command comprises a random read command. ### Claim 20 A method, comprising: receiving a write command comprising a logical address associated with a memory system comprising non-volatile memory cells; updating, at a buffer of the memory system, a mapping between the logical address and a physical address of the non-volatile memory cells based at least in part on receiving the write command; transferring information stored in the buffer to the non-volatile memory cells based at least in part on updating the information in the buffer; receiving a read command comprising the logical address based at least in part on updating the mapping between the logical address and the physical address of the non-volatile memory cells; and reading, using the updated mapping stored in the buffer of the memory system, the physical address of the non-volatile memory cells corresponding to the logical address based at least in part on receiving the read command.