# US 2024/0201853 A1 · Best read reference voltage search of 3d nand memory

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- Number: US 2024/0201853 A1
- Document ID: US20240201853A1
- Status: Published application
- Kind: A1
- Application number: 18/156,546
- Filed: 2023-01-19
- Published: 2024-06-20
- Earliest claimed: 2022-12-14
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Yufei FENG
- Web page: https://patentgrep.com/patent/US20240201853A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/12: Programming voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5634: Reference cells
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.

## Claims

### Claim 1

A method of a memory system, comprising:
determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage;
determining an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system;
determining a first scan range based on the anchor read reference voltage, wherein an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being a positive voltage value or a negative voltage value; and
determining a second best read offset of a second best read reference voltage with respect to the second read reference voltage based on the first scan range.

### Claim 2 (depends on 1)

The method of claim 1, wherein the determining the first best read offset includes:
determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset;
scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either 1 or 0;
for each first single read operation, determining:
a first bit count difference between the bit counts of the respective first single read operation and the previous first single read operation, if available, and
a second bit count difference between the bit counts of the respective first single read operation and the subsequent first single read operation, if available; and
determining the first read reference voltage of the first single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of first single read operations, to be a coarse best read reference voltage.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
when there are more than one first single read operations, of which sums of the respective first bit count differences and the respective second bit count differences have a same value, determining the first read reference voltage of the first single read operation, of which a minimum of the respective first bit count difference and the respective second bit count difference has a minimum value among the more than one first single read operations, to be the coarse best read reference voltage.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
determining a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; and
scanning the third scan range based on a fine step voltage by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either 1 or 0;
for each second single read operation, determining:
a first bit count difference between the bit counts of the respective second single read operation and the prior second single read operation, if available, and
a second bit count difference between the bit counts of the respective second single read operation and the subsequent second single read operation, if available; and
determining the second read reference voltage of the second single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of the second single read operations, to be the first best read reference voltage, an offset of the first best read reference voltage with respect to the first default read reference voltage being the first best read offset.

### Claim 5 (depends on 4)

The method of claim 4, wherein the determining the second best read offset of the second best read reference voltage with respect to the second default read reference voltage based on the first scan range includes:
scanning the first scan range by performing a series of third single read operations within the first scan range, each third single read operation corresponding to a third read reference voltage, each third single read operation generating a bit count of either 1 or 0;
for each third single read operation, determining:
a first bit count difference between the bit counts of the respective third single read operation and the prior third single read operation, if available, and
a second bit count difference between the bit counts of the respective third single read operation and the subsequent third single read operation, if available; and
determining the third read reference voltage of the third single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of third single read operations, to be the second best read reference voltage, an offset of the second best read reference voltage with respect to the second default read reference voltage being the second best read offset.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first, second, and third single read operations are partial page read operations.

### Claim 7 (depends on 2)

The method of claim 2, further comprising:
collecting a first set of first best read offsets, each first best read offset being a voltage shift of a best read reference voltage from the first default read reference voltage, each first best read offset corresponding to a memory cell condition that causes a set of memory cells under such memory cell condition to have the respective first best read offset, the first set of the first best read offsets each having a positive value or a negative value;
setting a maximum value of the first set of the first best read offsets to be the upper limit offset of the second scan range; and
setting a minimum value of the first set of the first best read offsets to be the lower limit offset of the second scan range.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
collecting a second set of second best read offsets, each second best read offset corresponding to one of the first set of the first best read voltages and the respective memory cell condition, each second best read offset being a voltage shift of a best read reference voltage from the second default read reference voltage, the second set of the second best read offsets each having a positive value or a negative value;
determining a difference between each pair of the first best read offset and the respective second best read offset, the difference being equal to the respective second best read offset minus the respective first best read offset;
setting a maximum value of the differences between each pair of the first best read offset and the respective second best read offset to be the upper limit offset of the first scan range; and
setting a minimum value of the differences between each pair of the first best read offset and the respective second best read offset to be the lower limit offset of the first scan range.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
determining an error correction code (ECC) decoding process is failed for reading the page before the determining the first best read offset of the first best read reference voltage with respect to the first default read reference voltage.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
performing an ECC soft decoding process to read the page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first or second default read reference voltage corresponds to default read reference voltage of the MLCs.

### Claim 12

A memory system, comprising:
a semiconductor memory device; and
a memory controller comprising circuitry configured to:
determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage;
determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in the semiconductor memory device;
determine a first scan range based on the anchor read reference voltage, wherein an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being a positive voltage value or a negative voltage value; and
determine a second best read offset of a second best read reference voltage with respect to the second read reference voltage based on the first scan range.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein the circuitry is further configured to:
determine a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset;
scan the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either 1 or 0;
for each first single read operation, determine:
a first bit count difference between the bit counts of the respective first single read operation and the previous first single read operation, if available, and
a second bit count difference between the bit counts of the respective first single read operation and the subsequent first single read operation, if available; and
determine the first read reference voltage of the first single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of first single read operations, to be a coarse best read reference voltage.

### Claim 14 (depends on 13)

The memory system of claim 13, wherein the circuitry is further configured to:
when there are more than one first single read operations, of which sums of the respective first bit count differences and the respective second bit count differences have a same value, determine the first read reference voltage of the first single read operation, of which a minimum of the respective first bit count difference and the respective second bit count difference has a minimum value among the more than one first single read operations, to be the coarse best read reference voltage.

### Claim 15 (depends on 13)

The memory system of claim 13, wherein the circuitry is further configured to:
determine a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; and
scan the third scan range based on a fine step voltage by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either 1 or 0;
for each second single read operation, determine:
a first bit count difference between the bit counts of the respective second single read operation and the prior second single read operation, if available, and
a second bit count difference between the bit counts of the respective second single read operation and the subsequent second single read operation, if available; and
determine the second read reference voltage of the second single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of the second single read operations, to be the first best read reference voltage, an offset of the first best read reference voltage with respect to the first default read reference voltage being the first best read offset.

### Claim 16

A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:
determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage;
determining an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device;
determining a first scan range based on the anchor read reference voltage, wherein an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being a positive voltage value or a negative voltage value; and
determining a second best read offset of a second best read reference voltage with respect to the second read reference voltage based on the first scan range.

### Claim 17 (depends on 16)

The non-transitory computer-readable medium of claim 16, wherein the determining the first best read offset includes:
determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset;
scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either 1 or 0;
for each first single read operation, determining:
a first bit count difference between the bit counts of the respective first single read operation and the previous first single read operation, if available, and a second bit count difference between the bit counts of the respective first single read operation and the subsequent first single read operation, if available; and
determining the first read reference voltage of the first single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of first single read operations, to be a coarse best read reference voltage.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the method further comprises:
when there are more than one first single read operations, of which sums of the respective first bit count differences and the respective second bit count differences have a same value, determining the first read reference voltage of the first single read operation, of which a minimum of the respective first bit count difference and the respective second bit count difference has a minimum value among the more than one first single read operations, to be the coarse best read reference voltage.

### Claim 19 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the method further comprises:
determining a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; and
scanning the third scan range based on a fine step voltage by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either 1 or 0;
for each second single read operation, determining:
a first bit count difference between the bit counts of the respective second single read operation and the prior second single read operation, if available, and
a second bit count difference between the bit counts of the respective second single read operation and the subsequent second single read operation, if available; and
determining the second read reference voltage of the second single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of the second single read operations, to be the first best read reference voltage, an offset of the first best read reference voltage with respect to the first default read reference voltage being the first best read offset.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the determining the second best read offset of the second best read reference voltage with respect to the second default read reference voltage based on the first scan range includes:
scanning the first scan range by performing a series of third single read operations within the first scan range, each third single read operation corresponding to a third read reference voltage, each third single read operation generating a bit count of either 1 or 0;
for each third single read operation, determining:
a first bit count difference between the bit counts of the respective third single read operation and the prior third single read operation, if available, and
a second bit count difference between the bit counts of the respective third single read operation and the subsequent third single read operation, if available; and
determining the third read reference voltage of the third single read operation, of which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of third single read operations, to be the second best read reference voltage, an offset of the second best read reference voltage with respect to the second default read reference voltage being the second best read offset.