# US 2024/0201852 A1 · Random data distribution

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- Number: US 2024/0201852 A1
- Document ID: US20240201852A1
- Status: Published application
- Kind: A1
- Application number: 18/067,744
- Filed: 2022-12-19
- Published: 2024-06-20
- Earliest claimed: 2022-12-19
- Assignees: GSI Technology, Inc.
- Applicants: GSI Technology Inc.
- Inventors: Avidan AKERIB
- Web page: https://patentgrep.com/patent/US20240201852A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for random data distribution in a memory array from a source row to a destination row includes receiving a plurality of pairs of addresses, where each pair includes a source address of a source cell in the source row and a destination addresses of a destination cell in a destination row, storing the source address in cells of a column associated with the destination cell, creating a Boolean algebra expression defining a correlation between each one of the source addresses and a value stored in each one of the source cells, where applying the Boolean algebra expression on any one of the source addresses provides a value of one of the source cells, concurrently applying the Boolean algebra expression on a plurality of columns storing the source addresses and concurrently writing a plurality of results on the destination row.

## Claims

### Claim 1

A method for random data distribution in a memory array from a source row to a destination row, the method comprising:
receiving a plurality of pairs of addresses, wherein each pair includes a source address of a source cell in said source row and a destination address of a destination cell in said destination row, wherein in each pair of addresses a value stored in said source cell is to be distributed to said destination cell;
for each one of said plurality of pairs of addresses, storing said source address in cells of a column associated with said destination cell;
creating a Boolean algebra expression defining a correlation between each one of said source addresses and a value stored in each one of said source cells, wherein applying said Boolean algebra expression on any one of said source addresses provides a value of said one of said source cells; and
concurrently, applying said Boolean algebra expression on a plurality of columns storing said source addresses and concurrently writing a plurality of results on said destination row, thereby distributing data from said source row to said destination row.

### Claim 2 (depends on 1)

The method of claim 1 wherein said applying said Boolean algebra expression further comprises concurrently activating a plurality of rows in said memory array.

### Claim 3 (depends on 2)

The method of claim 2 wherein said memory array comprises non-volatile memory cells.

### Claim 4 (depends on 2)

The method of claim 2 wherein said memory array comprises non-destructive memory cells.

### Claim 5 (depends on 1)

The method of claim 1 wherein said cells storing said source address and said destination cell are in a same column of a bit-processor unit.

### Claim 6 (depends on 1)

The method of claim 1 wherein said creating a Boolean algebra expression comprises using a Karnaugh map.

### Claim 7

A system for random data distribution from a plurality of source cells to a plurality of destination cells, the system comprising:
a memory array comprised of cells arranged in rows and columns;
a multiple bit-processor unit storing a plurality of source addresses of said plurality of said source cells in a plurality of columns, each source address in a column associated with one of said plurality of destination cells;
a Boolean expression builder to build a Boolean expression describing an association between said source addresses and a plurality of source values stored in said source cells; and
a data distributor to concurrently activate a plurality of cells on said columns according to said Boolean expression and to write a result provided on each one of said columns to one of said plurality of destination cells associated with said one of said columns.

### Claim 8 (depends on 7)

The system of claim 7 wherein said multiple bit-processor unit comprises a multiple row decoder to concurrently select a plurality of rows of said memory array according to said Boolean expression.

### Claim 9 (depends on 7)

The system of claim 7 wherein said memory array comprises non-volatile memory cells.

### Claim 10 (depends on 7)

The system of claim 7 wherein said memory array comprises non-destructive memory cells.