# US 2024/0201848 A1 · SSD with Reference Clock Loss Tolerant Oscillator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201848 A1 - Document ID: US20240201848A1 - Status: Published application - Kind: A1 - Application number: 18/349,906 - Filed: 2023-07-10 - Published: 2024-06-20 - Earliest claimed: 2022-12-15 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Nitin GUPTA; Pikul SARKAR; Bhavin ODEDARA - Web page: https://patentgrep.com/patent/US20240201848A1 ## CPC - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - H03L 7/099: concerning mainly the controlled oscillator of the loop - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/32: Timing circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Aspects of a storage device are provided for producing an oscillator clock from a host reference clock in a storage device lacking a crystal oscillator. The storage device includes a memory die, and an oscillator circuit that generates a clock based on a host reference clock and outputs an output clock to the memory die. While the host reference clock is available, the output clock includes a frequency that is identical to a frequency or a frequency division factor of the host reference clock. In response to loss of the host reference clock, the oscillator circuit reduces the frequency of the output clock to a frequency of the generated clock within a clock cycle following the loss of the host reference clock. In response to re-availability of the host reference clock, the oscillator circuit increases the frequency of the output clock back to the frequency of the host reference clock. ## Claims ### Claim 1 A storage device, comprising: a memory die; and a controller including an oscillator circuit configured to: generate a clock based on a host reference clock, and output an output clock to the memory die; wherein while the host reference clock is available, the output clock includes a frequency that is identical to a frequency or a division factor of the frequency of the host reference clock, and in response to loss of the host reference clock, the oscillator circuit is configured to reduce the frequency of the output clock to a frequency of the generated clock within a generated clock cycle following the loss of the host reference clock. ### Claim 2 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to increase the frequency of the output clock back to the frequency of the host reference clock in response to re-availability of the host reference clock following the loss. ### Claim 3 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to reduce the frequency of the output clock to the frequency of the generated clock without losing a lock status of a phase locked loop (PLL) coupled to the oscillator circuit. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to output the output clock to the memory die via a frequency multiplier circuit configured to multiply the frequency of the output clock. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the oscillator circuit includes a clock generation circuit configured to generate the clock based on the host reference clock, and a clock selection circuit configured to select the output clock from the host reference clock or the generated clock. ### Claim 6 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to select the output clock from the generated clock in response to the loss of the host reference clock. ### Claim 7 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to select a positive edge of the output clock from the host reference clock in response to an availability of the host reference clock. ### Claim 8 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to shift a phase of the host reference clock a plurality of times. ### Claim 9 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to detect a loss of the host reference clock. ### Claim 10 (depends on 1) The storage device of claim 1, wherein the oscillator circuit is configured to generate a reference sense signal indicating an availability of the host reference clock. ### Claim 11 (depends on 1) The storage device of claim 1, wherein during a time period in which the host reference clock is available, a positive edge of the output clock is aligned in time with a positive edge of the host reference clock and a negative edge of the output clock is aligned in time with a negative edge of the generated clock during a respective clock cycle of the host reference clock, and during a time period in which the host reference clock is lost, a positive edge of the output clock is aligned in time with a positive edge of the generated clock within a generated clock cycle following the loss of the host reference clock. ### Claim 12 A storage device, comprising: a memory die; and an oscillator circuit configured to: generate a clock based on a host reference clock, and output an output clock to the memory die; wherein while the host reference clock is available, a positive edge of the output clock is aligned in time with a positive edge of the host reference clock and a negative edge of the output clock is aligned in time with a negative edge of the generated clock during a respective clock cycle of the host reference clock, and in response to loss of the host reference clock, a positive edge of the output clock is aligned in time with a positive edge of the generated clock within a generated clock cycle following the loss. ### Claim 13 (depends on 12) The storage device of claim 12, wherein the oscillator circuit is configured to shift a phase of the host reference clock, and to output the negative edge of the generated clock based on the shifted phase. ### Claim 14 (depends on 12) The storage device of claim 12, wherein the oscillator circuit is configured to trim the generated clock at a lower frequency than a frequency of the host reference clock to compensate for process variations. ### Claim 15 (depends on 12) The storage device of claim 12, wherein the oscillator circuit is configured to generate a reference sense signal indicating an availability of the host reference clock for a plurality of host reference cycles, and to select the positive edge of the host reference clock as the output clock following occurrence of the plurality of host reference cycles. ### Claim 16 (depends on 12) The storage device of claim 12, wherein the oscillator circuit is configured to detect loss of the host reference clock, and to reduce a frequency of the output clock to a frequency of the generated clock within a generated clock cycle following the detection. ### Claim 17 (depends on 12) The storage device of claim 12, wherein the oscillator circuit is configured to increase a frequency of the output clock to the frequency of the host reference clock in response to an availability of the host reference clock without losing a lock status of a phase locked loop (PLL) coupled to the oscillator circuit. ### Claim 18 A storage device, comprising: a memory die; and an oscillator circuit configured to: generate a clock based on a host reference clock, and output an output clock to the memory die; wherein while the host reference clock is available, the oscillator circuit is configured to output the output clock at a frequency that is identical to a frequency of the host reference clock or a division factor of the frequency of the host reference clock, in response to loss of the host reference clock, the oscillator circuit is configured to reduce the frequency of the output clock to a frequency of the generated clock within a generated clock cycle following the loss, and in response to re-availability of the host reference clock, the oscillator circuit is configured to increase the frequency of the output clock back to the frequency of the host reference clock within a plurality of host reference clock cycles following the re-availability. ### Claim 19 (depends on 18) The storage device of claim 18, wherein during a time period in which the host reference clock is available, the oscillator circuit is configured to align a positive edge of the output clock in time with a positive edge of the host reference clock and to align a negative edge of the output clock in time with a negative edge of the generated clock during a respective clock cycle of the host reference clock, and during a time period in which the host reference clock is lost, the oscillator circuit is configured to align a positive edge of the output clock in time with a positive edge of the generated clock within a generated clock cycle following the loss of the host reference clock. ### Claim 20 (depends on 18) The storage device of claim 18, wherein the storage device lacks a crystal oscillator.