# US 2024/0201774 A1 · Storage controller, storage device including the same, and operation method of storage controller

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- Number: US 2024/0201774 A1
- Document ID: US20240201774A1
- Status: Published application
- Kind: A1
- Application number: 18/589,263
- Filed: 2024-02-27
- Published: 2024-06-20
- Earliest claimed: 2017-12-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyun Ju Yi; Jaeho Sim; Kicheol Eom; Dong-Ryoul Lee; Hyotaek Leem
- Web page: https://patentgrep.com/patent/US20240201774A1

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4243: {with synchronous protocol}
- G06F 13/4273: {using a clocked protocol}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

## Claims

### Claim 1

A storage controller configured to control a nonvolatile memory device, the storage controller comprising:
a physical layer configured to communicate with a host device based on a nonvolatile memory express (NVMe) interface;
a command fetching block configured to use a first clock to fetch a command from a submission queue of the host device;
a control block configured to use a second clock to execute the command;
a completion block configured to use a third clock to write completion information in a completion queue of the host device;
a clock managing block configured to provide the first to third clocks to the command fetching block, the control block, and the completion block,
wherein the clock managing block includes:
a reference clock generator configured to generate a reference clock;
an enable signal generator configured to generate first to third enable signals based on operation states of the command fetching block, the control block, and the completion block, respectively;
a plurality of logic circuits configured to output the first to third clocks to the command fetching block, the control block, and the completion block, based on the reference clock and the first to third enable signals, respectively.

### Claim 2 (depends on 1)

The storage controller of claim 1, wherein a first logic circuit of the plurality of logic circuits is configured to output the first clock to the command fetching block while the command fetching block fetches the command,
a second logic circuit of the plurality of logic circuits is configured to output the second clock to the control block while the control block executes the command, and
a third logic circuit of the plurality of logic circuits is configured to output the third clock to the control block while the completion block writes the completion information in the completion queue.

### Claim 3 (depends on 2)

The storage controller of claim 2, wherein the first logic circuit is further configured to deactivate the first clock when the command fetching block completely fetches the command,
the second logic circuit is further configured to deactivate the second clock when the control block completely executes the command, and
the third logic circuit is further configured to deactivate the third clock when the completion block completely writes the completion information in the completion queue.

### Claim 4 (depends on 1)

The storage controller of claim 1, further comprising:
a system bus configured to be connected with the physical layer,
wherein the enable signal generator is further configured to detect information exchanged through the system bus and determine the operation states of the command fetching block, the control block, and the completion block based on the detected information.

### Claim 5 (depends on 1)

The storage controller of claim 1, further comprising:
a direct memory access (DMA) engine configured to use a fourth clock to process a DMA operation of exchanging data with the host device,
wherein the clock managing block is further configured to provide the fourth clock based on an operation state state of the DMA engine.

### Claim 6 (depends on 1)

The storage controller of claim 1, further comprising:
an interrupt block configured to use a fifth clock to transmit an interrupt signal to the host device, after the completion block writes the completion information in the completion queue of the host device,
wherein the clock managing block is further configured to provide the fifth clock to the interrupt block based on an operation state of the interrupt block.

### Claim 7 (depends on 1)

The storage controller of claim 1, further comprising:
a control register block configured to use a sixth clock to receive a notification through a doorbell signaling form the host device, and
wherein the clock managing block is further configured to provide the sixth clock to the control register block based on an operation state of the control register block.

### Claim 8 (depends on 7)

The storage controller of claim 7, wherein the command fetching block is configured to fetch the command from the submission queue of the host device in response to the notification.

### Claim 9 (depends on 1)

The storage controller of claim 1, wherein the command fetching block is configured to fetch the command by transmitting a memory read request to the host device and receiving the command from the host device.

### Claim 10 (depends on 9)

The storage controller of claim 9, wherein the clock managing block is further configured to deactivate the second clock from a first time to transmit the memory read request, to a second time to receive the command.

### Claim 11

An operation method of a storage controller configured to control a nonvolatile memory device, the operation method comprising:
fetching a command from a submission queue of the host device through a physical layer using a first clock, wherein the first clock being activated based on a reference clock during the fetching the command;
executing the fetched command using a second clock, wherein the second clock being activated based on the reference clock during the executing the fetched command; and
writing completion information in a completion queue of the host device through the physical layer using a third clock, wherein the third clock being activated based on the reference clock during the writing the completion information, and
wherein the storage controller communicates with the host device, based on a nonvolatile memory express (NVMe) interface.

### Claim 12 (depends on 11)

The operation method of claim 11, wherein the fetching the command comprises:
transmitting a memory read request to the host device; and
receiving the command from the host device.

### Claim 13 (depends on 12)

The operation method of claim 12, wherein the first clock is deactivated from a time to transmit the memory read request to a time to receive the command.

### Claim 14 (depends on 11)

The operation method of claim 11, further comprising:
performing a direct memory access (DMA) operation using a fourth clock, wherein the fourth clock activating during the performing the DMA operation based on the reference clock.

### Claim 15 (depends on 11)

The operation method of claim 11, wherein the first clock is deactivated when the fetching command is completed,
the second clock is deactivated when the executing the fetched command is completed, and
the third clock is deactivated when the writing the completion information is completed.

### Claim 16

A storage controller configured to control a nonvolatile memory device, the storage controller comprising:
a physical layer configured to communicate with a host device based on a nonvolatile memory express (NVMe) interface;
a command fetching block configured to use a first clock to fetch a command from a submission queue of the host device;
a control block configured to use a second clock to execute the command;
a direct memory access (DMA) block configured to use a third clock to perform a DMA operation; and
a clock managing block configured to:
provide the command fetching block, the control block, and the DMA block with the first to third clocks based on a reference clock, respectively; and
deactivate the first to third clocks based on operation states of the command fetching block, the control block, and the DMA block, respectively.

### Claim 17 (depends on 16)

The storage controller of claim 16, wherein the clock managing block comprises:
a reference clock generator configured to the reference clock;
an enable signal generator configured to generate first to third enable signals based on operation states of the command fetching block, the control block, and the DMA block; and
a plurality of logic circuits configured to output the first to third clocks based on the reference clock and deactivate the first to third clocks based on the first to third enable signals, respectively.

### Claim 18 (depends on 16)

The storage controller of claim 16, wherein a first logic circuit of the plurality of logic circuits is configured to deactivate the first clock after the command fetching block completely fetches the command,
a second logic circuit of the plurality of logic circuits is configured to deactivate the second clock after the control block completely execute the command, and
a third logic circuit of the plurality of logic circuits is configured to deactivate the third clock after the DMA block completely perform the DMA operation.

### Claim 19 (depends on 16)

The storage controller of claim 16, wherein the clock managing block deactivates the first clock depending on an overhead of the host device, while the command fetching block fetches the command.

### Claim 20 (depends on 16)

The storage controller of claim 16, wherein the clock managing block deactivates the second clock depending on an overhead of the host device or an overhead of the nonvolatile memory device, while a control block executes the command.