# US 2024/0201766 A1 · System-on-Chip with DVFM Protection Circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201766 A1 - Document ID: US20240201766A1 - Status: Published application - Kind: A1 - Application number: 18/522,324 - Filed: 2023-11-29 - Published: 2024-06-20 - Earliest claimed: 2022-02-17 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Doron Rajwan; Ami Schwartzman; Lior Zimet - Web page: https://patentgrep.com/patent/US20240201766A1 ## CPC - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/324: by lowering clock frequency - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3296: by lowering the supply or operating voltage - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid. ## Claims ### Claim at position 1 1-15. (canceled) ### Claim 16 A system, comprising: multiple hardware circuits, which are coupled to respective power domains having respective sets of domain-specific power settings; and protection circuitry, configured to: monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings; determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions; and grant the requested transitions in response to verifying that all the system-level combinations in the subset are specified as valid. ### Claim 17 (depends on 16) The system according to claim 16, wherein a given domain-specific power setting comprises multiple control parameters. ### Claim 18 (depends on 17) The system according to claim 17, wherein the multiple control parameters comprise at least a voltage and a clock rate for the respective power domain. ### Claim 19 (depends on 16) The system according to claim 16, wherein the protection circuitry is configured to initiate a responsive action in response to verifying that at least one of the system-level combinations in the subset is specified as invalid. ### Claim 20 (depends on 19) The system according to claim 19, wherein the responsive action comprises halting at least part of the system. ### Claim 21 (depends on 16) The system according to claim 16, wherein, in the requests, the hardware circuits are configured to specify requested domain-specific power settings using indices having a defined order. ### Claim 22 (depends on 21) The system according to claim 21, wherein, for first and second power domains among the multiple power domains, the protection circuitry is configured to detect that a given system-level combination of domain-specific power settings is valid, by detecting that: a first index, of a domain-specific power setting requested for the first power domain, is lower than a first predefined threshold; and a second index, of a domain-specific power setting requested for the second power domain, is higher than a second predefined threshold. ### Claim 23 (depends on 16) The system according to claim 16, wherein the protection circuitry is configured to: while a first transition is in progress in a first power domain, receive a second request for a second transition in a second power domain; and upon detecting that the second transition potentially causes an invalid system-level combination, defer the second request and re-evaluate the second request only after the first transition is completed. ### Claim 24 A method, comprising: operating multiple hardware circuits, which are coupled to respective power domains having respective sets of domain-specific power settings; monitoring requests in which one or more of the hardware circuits request transitions between the domain-specific power settings; determining, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions; and granting the requested transitions in response to verifying that all the system-level combinations in the subset are specified as valid. ### Claim 25 (depends on 24) The method according to claim 24, wherein a given domain-specific power setting comprises multiple control parameters. ### Claim 26 (depends on 25) The method according to claim 25, wherein the multiple control parameters comprise at least a voltage and a clock rate for the respective power domain. ### Claim 27 (depends on 24) The method according to claim 24, further comprising initiating a responsive action in response to verifying that at least one of the system-level combinations in the subset is specified as invalid. ### Claim 28 (depends on 24) The method according to claim 24, wherein the requests specify requested domain-specific power settings using indices having a defined order. ### Claim 29 (depends on 28) The method according to claim 28, wherein, for first and second power domains among the multiple power domains, detecting that a given system-level combination of domain-specific power settings is valid comprises detecting that: a first index, of a domain-specific power setting requested for the first power domain, is lower than a first predefined threshold; and a second index, of a domain-specific power setting requested for the second power domain, is higher than a second predefined threshold. ### Claim 30 (depends on 24) The method according to claim 24, further comprising: while a first transition is in progress in a first power domain, receiving a second request for a second transition in a second power domain; and upon detecting that the second transition potentially causes an invalid system-level combination, deferring the second request and re-evaluate the second request only after the first transition is completed. ### Claim 31 A System-on-Chip (SoC), comprising: multiple hardware circuits, which are coupled to respective power domains having respective sets of domain-specific power settings; and protection circuitry, configured to: monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings; determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions; and grant the requested transitions in response to verifying that all the system-level combinations in the subset are specified as valid. ### Claim 32 (depends on 31) The SoC according to claim 31, wherein the hardware circuits comprise at least a memory controller, one or more processors and a communication fabric. ### Claim 33 (depends on 31) The SoC according to claim 31, further comprising a controller configured to run Dynamic Voltage and Frequency Management (DVFM) software that receives the requests from the one or more of the hardware circuits, and performs or denies the requests. ### Claim 34 (depends on 33) The SoC according to claim 33, wherein the protection circuitry is configured to operate in parallel to the DVFM software, and to deny at least one request that is not denied by the DVFM software. ### Claim 35 (depends on 33) The SoC according to claim 33, wherein the protection circuitry is configured to halt at least part of the SoC in response to detecting a request that (i) causes traversal of an invalid system-level combination, but (ii) is not denied by the DVFM software.