# US 2024/0201718 A1 · Method for implementing an i/o buffer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2024/0201718 A1
- Document ID: US20240201718A1
- Status: Published application
- Kind: A1
- Application number: 18/082,921
- Filed: 2022-12-16
- Published: 2024-06-20
- Earliest claimed: 2022-12-16
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Sasi Rama Subrahmanyam LANKA; Vss Prasad Babu AKURATHI; Hari Bilash DUBEY
- Web page: https://patentgrep.com/patent/US20240201718A1

## CPC

- G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence)
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 17/6874: {in a symmetrical configuration}
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.

## Claims

### Claim 1

An input/output (I/O) buffer comprising:
a connection to a VCCO power supply;
a connection to a VCCINT power supply;
a connection to a reference voltage;
a VCCO detection circuit coupled to a bias generation circuit;
a transmitter circuit coupled to the bias generation circuit, the transmitter circuit having a single-stage level-shifter circuit, wherein the VCCO detection circuit is coupled to the single-stage level-shifter circuit through the bias generation circuit such that core power domain data is level-shifted to a VCCO I/O buffer power domain; and
a receiver circuit coupled to an I/O pad.

### Claim 2 (depends on 1)

The I/O buffer of claim 1, wherein the bias generation circuit further comprises a plurality of resistor divider circuits configured to generate bias voltages using the VCCO power supply.

### Claim 3 (depends on 1)

The I/O buffer of claim 1, wherein the VCCO detection circuit is configured to produce low voltage and high voltage VCCO detect signals.

### Claim 4 (depends on 1)

The I/O buffer of claim 1, wherein the VCCO detection circuit further comprises:
a resistor divider circuit;
a plurality of two stage comparator circuits coupled to the VCCINT power supply; and
a plurality of buffers.

### Claim 5 (depends on 4)

The I/O buffer of claim 4, wherein each two-stage comparator circuit further comprises:
a NMOS differential transistor pair;
a PMOS common source amplifier; and
a differential to CMOS converting stage.

### Claim 6 (depends on 1)

The I/O buffer of claim 1, wherein the transmitter circuit further comprises:
a control logic circuit configured to decide I/O buffer modes;
an on-die termination circuit; and
an I/O pad connection.

### Claim 7 (depends on 1)

The I/O buffer of claim 1, wherein the transmitter circuit further comprises:
a control logic circuit configured to decide I/O buffer modes;
a plurality of pre-driver circuits coupled to the single-stage level-shifter circuit; and
a driver circuit coupled to the pre-driver circuits.

### Claim 8 (depends on 7)

The I/O buffer of claim 7, wherein an output of the single-stage level-shifter circuit is fed directly into a pre-driver circuit acting as a high-voltage buffer.

### Claim 9 (depends on 7)

The I/O buffer of claim 7, wherein the single-stage level-shifter circuit further comprises a high voltage level-shifter circuit.

### Claim 10 (depends on 7)

The I/O buffer of claim 7, wherein the pre-driver circuits further comprise a P pre-driver and an N pre-driver.

### Claim 11

An input/output (I/O) buffer comprising:
a connection to a VCCO power supply;
a connection to a VCCINT power supply;
a connection to a reference voltage;
a data input coupled to a control logic circuit;
a plurality of control signals coupled to the control logic circuit;
a single-stage level-shifter circuit;
pre-driver circuits coupled to the single-stage level-shifter circuit;
driver circuits coupled to the pre-driver circuits;
a bias generation circuit coupled to the driver circuits;
a VCCO detection circuit coupled to the single-stage level-shifter circuit through the bias generation circuit such that core power domain data is level-shifted to a VCCO I/O buffer power domain; and
a receiver circuit coupled to an I/O pad.

### Claim 12

A method for implementing an input/output (I/O) buffer comprising:
connecting to a VCCO power supply;
connecting to a VCCINT power supply;
receiving a reference voltage (REF) in a VCCO detection circuit;
transmitting VCCO detect signals from the VCCO detection circuit to a bias generation circuit;
receiving bias voltages in a transmitter circuit from the bias generation circuit, the transmitter circuit having a single-stage level-shifter circuit, wherein the VCCO detection circuit is coupled to the single-stage level-shifter circuit through the bias generation circuit; and
receiving data in a receiver from an I/O pad.

### Claim 13 (depends on 12)

The method of claim 12, wherein the bias generation circuit further comprises a plurality of resistor divider circuits configured to generate bias voltages using the VCCO power supply.

### Claim 14 (depends on 12)

The method of claim 12, wherein the VCCO detection circuit is configured to produce low voltage and high voltage VCCO detect signals.

### Claim 15 (depends on 12)

The method of claim 12, wherein the VCCO detection circuit further comprises:
a resistor divider circuit;
a plurality of two stage comparator circuits coupled to the VCCINT power supply; and
a plurality of buffers.

### Claim 16 (depends on 15)

The method of claim 15, wherein the two stage comparator circuits further comprise:
NMOS differential transistor pairs;
PMOS common source amplifiers; and
differential to CMOS converting stages.

### Claim 17 (depends on 12)

The method of claim 12, wherein the transmitter circuit further comprises:
a plurality of pre-driver circuits coupled to the single-stage level-shifter circuit; and
a driver circuit coupled to the pre-driver circuits.

### Claim 18 (depends on 17)

The method of claim 17, wherein the transmitter circuit further comprises:
a control logic circuit configured to decide I/O buffer modes;
an on-die termination circuit; and
an I/O pad connection.

### Claim 19 (depends on 12)

The method of claim 12, wherein an output of the single-stage level-shifter circuit is fed directly into a pre-driver circuit acting as a high-voltage buffer.

### Claim 20 (depends on 12)

The method of claim 12, wherein the single-stage level-shifter circuit comprises a high voltage level-shifter circuit.