# US 2024/0201525 A1 · Engineered electro-optic devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201525 A1 - Document ID: US20240201525A1 - Status: Published application - Kind: A1 - Application number: 18/544,220 - Filed: 2023-12-18 - Published: 2024-06-20 - Earliest claimed: 2019-10-29 - Assignees: Psiquantum, Corp. - Applicants: Psiquantum, Corp. - Inventors: Yong Liang; Mark G. Thompson; Chia-Ming Chang; Vimal Kumar Kamineni - Web page: https://patentgrep.com/patent/US20240201525A1 ## CPC - G02F 1/035: in an optical waveguide structure - G02F 1/0027: {Ferro-electric materials} - G02F 1/05: with ferro-electric properties (G02F1/035, G02F1/055 take precedence) - G02F 1/225: in an optical waveguide structure - G02B 2006/12142: {Modulator} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS ## Abstract A system includes a classical computing system and one or more quantum computing chips coupled to the classical computing system. The one or more quantum computing chips includes one or more electro-optic devices. Each electro-optic device includes a substrate, a waveguide disposed on top of the substrate, and a layer stack disposed on top of the waveguide and including a plurality of electro-optic material layers interleaved with a plurality of interlayers. Each electro-optic device further comprising a waveguide core disposed on top of a portion of the layer stack. The plurality of interlayers are characterized by a first lattice structure and the plurality of electro-optic material layers are under tensile stress and are characterized by a second lattice structure and crystallographic phase. ## Claims ### Claim 1 A system comprising: a classical computing system; and one or more quantum computing chips coupled to the classical computing system, wherein the one or more quantum computing chips includes one or more electro-optic devices, each electro-optic device of the one or more electro-optic devices comprising: a substrate; a waveguide disposed on top of the substrate; a layer stack disposed on top of the waveguide and including a plurality of electro-optic material layers interleaved with a plurality of interlayers; and a waveguide core disposed on top of a portion of the layer stack; wherein the plurality of interlayers are characterized by a first lattice structure; and wherein the plurality of electro-optic material layers are under tensile stress and are characterized by a second lattice structure and crystallographic phase. ### Claim 2 (depends on 1) The system of claim 1, wherein the plurality of interlayers maintains a first lattice structure at a room temperature and at a cryogenic temperature, and wherein the plurality of electro-optic material layers are under tensile stress and maintain a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature. ### Claim 3 (depends on 1) The system of claim 1, further comprising at least one electronic component. ### Claim 4 (depends on 3) The system of claim 3, wherein the at least one electronic component includes at least one of a pulsed pump laser or a microwave oscillator. ### Claim 5 (depends on 1) The system of claim 1, wherein the one or more quantum computing chips each includes at least one of a hybrid electronic chip or an integrated photonics chip. ### Claim 6 (depends on 1) The system of claim 1, further comprising a user device communicatively coupled to at least one of the classical computing system or the one or more quantum computing chips. ### Claim 7 (depends on 1) The system of claim 1, further comprising networking hardware coupled to the one or more quantum computing chips. ### Claim 8 (depends on 7) The system of claim 7, wherein the networking hardware is coupled to the one or more quantum computing chips via optical interconnects. ### Claim 9 (depends on 1) The system of claim 1, further comprising a cryostat, wherein the one or more quantum computing chips are housed within the cryostat and the cryostat is configured to operate between about 340° K and 4° K. ### Claim 10 (depends on 1) The system of claim 1, wherein the plurality of electro-optic material layers includes at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb, La)(Zr,Ti)O3. ### Claim 11 (depends on 1) The system of claim 1, wherein the plurality of interlayers includes at least one of MgO, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrZrO3, or SrNbO3. ### Claim 12 A method of operating a hybrid quantum computing system, the method comprising: providing a classical computing system; providing one or more quantum computing chips coupled to the classical computing system, wherein the one or more quantum computing chips includes one or more electro-optic devices, each electro-optic device of the one or more electro-optic devices comprising: a substrate; a waveguide disposed on top of the substrate; a layer stack disposed on top of the waveguide and including a plurality of electro-optic material layers interleaved with a plurality of interlayers; and a waveguide core disposed on top of a portion of the layer stack; wherein the plurality of interlayers are characterized by a first lattice structure; and wherein the plurality of electro-optic material layers are under tensile stress and are characterized by a second lattice structure and crystallographic phase; and performing one or more quantum computing processes using the one or more quantum computing chips. ### Claim 13 (depends on 12) The method of claim 12, further comprising: providing a cryostat; and housing the one or more quantum computing chips in the cryostat. ### Claim 14 (depends on 12) The method of claim 12, further comprising reducing a temperature of the one or more quantum computing chips to about 4° K. ### Claim 15 (depends on 14) The method of claim 14, wherein reducing the temperature of the one or more quantum computing chips occurs prior to performing the one or more quantum computing processes using the one or more quantum computing chips. ### Claim 16 (depends on 12) The method of claim 12, further comprising increasing a temperature of the one or more quantum computing chips to about 340° K. ### Claim 17 (depends on 12) The method of claim 12, wherein the plurality of interlayers maintains a first lattice structure at a room temperature and at a cryogenic temperature, and wherein the plurality of electro-optic material layers are under tensile stress and maintain a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature. ### Claim 18 (depends on 12) The method of claim 12, further comprising providing a user device communicatively coupled to at least one of the classical computing system or the one or more quantum computing chips. ### Claim 19 (depends on 12) The method of claim 12, further comprising providing networking hardware coupled to the one or more quantum computing chips. ### Claim 20 (depends on 19) The method of claim 19, wherein the networking hardware is coupled to the one or more quantum computing chips via optical interconnects.