# US 2024/0201458 A1 · Optical integrated circuit structure including edge coupling protective features and method of forming same

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- Number: US 2024/0201458 A1
- Document ID: US20240201458A1
- Status: Published application
- Kind: A1
- Application number: 18/589,180
- Filed: 2024-02-27
- Published: 2024-06-20
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Chen-Hao Huang; Sui-Ying Hsu; YuehYing Lee; Chia-Ping Lai; Chien-Ying Wu; Hau-Yan Lu
- Web page: https://patentgrep.com/patent/US20240201458A1

## CPC

- G02B 6/4248: {Feed-through connections for the hermetical passage of fibres through a package wall (see provisionally also G02B6/4428)}
- G02B 6/12: of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00)
- G02B 6/12002: {Three-dimensional structures}
- G02B 6/12004: {Combinations of two or more optical elements}
- G02B 6/136: by etching
- G02B 6/4206: {Optical features (G02B6/4207, G02B6/421 take precedence)}
- G02B 6/4274: {Electrical aspects (G02B6/4263 and G02B6/4265 take precedence)}
- H10W 20/4421: {the principal metal being copper}
- G02B 6/30: for use between fibre and thin-film device
- G02B 6/4228: {Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements (G02B6/4234 takes precedence)}
- G02B 6/4236: {Fixing or mounting methods of the aligned elements}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10W 20/42: Vias, e.g. via plugs
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

## Claims

### Claim 1

An optical integrated circuit (IC) structure comprising:
a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;
a bottom oxide layer disposed on the substrate;
a semiconductor layer disposed on the bottom oxide layer; and
vents that extend through the semiconductor layer and the bottom oxide layer to expose the undercut.

### Claim 2 (depends on 1)

The IC structure of claim 1, further comprising:
a dielectric structure disposed on the semiconductor layer;
an interconnect structure disposed in the dielectric structure; and
a barrier ring disposed in the dielectric structure and surrounding the interconnect structure.

### Claim 3 (depends on 2)

The IC structure of claim 2, wherein the barrier ring separates the interconnect structure from the vents and the fiber slot, and the barrier ring is configured to prevent contaminants from diffusing into the interconnect structure.

### Claim 4 (depends on 2)

The IC structure of claim 2, wherein:
the barrier ring and the interconnect structure comprise copper or a copper alloy; and
the barrier ring has a thickness of at least 10 microns.

### Claim 5 (depends on 2)

The IC structure of claim 2, further comprising a fiber cavity that extends through the semiconductor layer and the bottom oxide layer to expose the fiber slot.

### Claim 6 (depends on 1)

The IC structure of claim 1, wherein a portion of the semiconductor layer that is disposed over the undercut and extends between the vents is configured to operate as an optical waveguide.

### Claim 7 (depends on 1)

The IC structure of claim 1, further comprising a barrier layer disposed on surfaces of the vents, the undercut, and the fiber slot.

### Claim 8 (depends on 7)

The IC structure of claim 7, wherein the barrier layer comprises a dielectric material.

### Claim 9 (depends on 8)

The IC structure of claim 8, wherein the barrier layer has a thickness of at least 10 microns.

### Claim 10

An optical integrated circuit (IC) structure comprising:
a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;
a semiconductor layer disposed on the substrate;
a dielectric structure disposed on the semiconductor layer;
vents that extend through a coupling region of the dielectric structure and expose the undercut; and
a dielectric material disposed on surfaces of the vents, the undercut, and the fiber slot.

### Claim 11 (depends on 10)

The IC structure of claim 10, wherein the dielectric material has a thickness of at least 50 nanometers.

### Claim 12 (depends on 10)

The IC structure of claim 10, further comprising:
an interconnect structure disposed in the dielectric structure; and
a barrier ring disposed in the dielectric structure and surrounding the interconnect structure.

### Claim 13 (depends on 12)

The IC structure of claim 12, wherein the barrier ring and the interconnect structure comprise copper or a copper alloy.

### Claim 14 (depends on 12)

The IC structure of claim 12, further comprising a fiber cavity that extends through the dielectric structure and exposes the fiber slot.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein:
the dielectric material is disposed on surfaces of the fiber cavity; and
the barrier ring contacts the dielectric material on opposing sides of the fiber cavity.

### Claim 16 (depends on 10)

The IC structure of claim 10, wherein the substrate comprises an optical waveguide that is disposed over the undercut and that extends between the vents to the fiber slot.

### Claim 17

An optical integrated circuit (IC) structure comprising:
a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;
a semiconductor layer disposed on the substrate and comprising an optical waveguide disposed over the undercut;
inter-metal dielectric (IMD) layers disposed on the semiconductor layer; and
vents that extend through the IMD layers and the semiconductor layer to expose the undercut.

### Claim 18 (depends on 17)

The IC structure of claim 17, further comprising:
a fiber cavity that extends through the IMD layers and the semiconductor layer to expose the fiber slot; and
a barrier layer disposed on surfaces of the vents, the undercut, the fiber slot, and the fiber cavity.

### Claim 19 (depends on 17)

The IC structure of claim 17, wherein the optical waveguide is disposed between the vents.

### Claim 20 (depends on 17)

The IC structure of claim 17, further comprising:
an interconnect structure disposed in the IMD layers; and
a barrier ring disposed in the IMD layers and surrounding the interconnect structure.