# US 2024/0201444 A1 · Chiplet communication using an optical communication substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0201444 A1 - Document ID: US20240201444A1 - Status: Published application - Kind: A1 - Application number: 18/542,974 - Filed: 2023-12-18 - Published: 2024-06-20 - Earliest claimed: 2022-12-19 - Assignees: Lightmatter, Inc. - Applicants: Lightmatter, Inc. - Inventors: Clifford Chao; Darius Bunandar - Web page: https://patentgrep.com/patent/US20240201444A1 ## CPC - G02B 6/3596: {With planar waveguide arrangement, i.e. in a substrate, regardless if actuating mechanism is outside the substrate} - G02B 6/43: Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections - G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package} - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface. ## Claims ### Claim 1 A computing system comprising: a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer; an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface. ### Claim 2 (depends on 1) The computing system of claim 1, wherein each port of the first and second pluralities of ports comprises: an electric connection connecting the surface of the electronic die to the interposer; and a SerDes coupled to the electric connection. ### Claim 3 (depends on 2) The computing system of claim 2, wherein the SerDes is formed on the electronic die. ### Claim 4 (depends on 3) The computing system of claim 3, wherein the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, wherein the SerDes couples to either the TIA, the modulator driver, or both. ### Claim 5 (depends on 1) The computing system of claim 1, wherein at least one port of the outer interface is positioned within 1 mm of an outer perimeter of the electronic die. ### Claim 6 (depends on 5) The computing system of claim 5, wherein at least one port of the inner interface is positioned more than 1 mm away from the outer perimeter of the electronic die. ### Claim 7 (depends on 1) The computing system of claim 1, wherein the surface of the electronic die is between 25 mm2 and 625 mm2. ### Claim 8 (depends on 1) The computing system of claim 1, wherein the inner interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer. ### Claim 9 (depends on 1) The computing system of claim 1, wherein the photonic interposer further comprises an off-chip optical coupler, wherein the photonic network couples the off-chip optical coupler to at least one port of the inner interface. ### Claim 10 (depends on 1) The computing system of claim 1, wherein each port of the first and second pluralities of ports comprises an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface. ### Claim 11 A computing system comprising: a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches, the photonic interposer having a surface configured to bond to an electronic die; and an interface comprising a 2-dimensional array of ports configured to electrically couple the electronic die to the photonic interposer when the electronic die is bonded to the surface of the photonic interposer, wherein the array is arranged with at least three columns and at least three rows of ports. ### Claim 12 (depends on 11) The computing system of claim 11, wherein each port of the 2-dimensional array comprises: an electric connection configured to connect the electronic die to the surface of the interposer; and a SerDes coupled to the electric connection. ### Claim 13 (depends on 12) The computing system of claim 12, wherein the SerDes is formed on the electronic die. ### Claim 14 (depends on 13) The computing system of claim 13, wherein the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, wherein the SerDes couples to either the TIA, the modulator driver, or both. ### Claim 15 (depends on 11) The computing system of claim 11, wherein at least one port of the inner interface is positioned more than 1 mm away from an outer perimeter of the electronic die when the electronic die is bonded to the surface of the photonic interposer. ### Claim 16 (depends on 11) The computing system of claim 11, wherein the photonic interposer further comprises an off-chip optical coupler, wherein the photonic network couples the off-chip optical coupler to at least one port of the 2-dimensional array. ### Claim 17 (depends on 11) The computing system of claim 11, wherein each port of the 2-dimensional array comprises an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface. ### Claim 18 A method for manufacturing a computing system, comprising: obtaining a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; bonding an electronic die to the photonic interposer through a surface of the electronic die, wherein the bonding comprises connecting the electronic die to the photonic interposer using: an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface. ### Claim 19 (depends on 18) The method of claim 18, wherein at least one port of the outer interface is positioned within 1 mm of an outer perimeter of the electronic die. ### Claim 20 (depends on 19) The method of claim 19, wherein at least one port of the inner interface is positioned more than 1 mm away from the outer perimeter of the electronic die. ### Claim 21 (depends on 20) The method of claim 20, wherein the surface of the electronic die is between 25 mm2 and 625 mm2. ### Claim 22 A computing system comprising: a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; a first electronic die having a first surface bonded to the photonic interposer, the first electronic die having: a first inner interface comprising a first plurality of ports electrically coupling the first electronic die to the photonic interposer; and a first outer interface comprising a second plurality of ports electrically coupling the first electronic die to the photonic interposer, wherein the first outer interface at least partially encloses the first inner interface; and a second electronic die having a surface bonded to the photonic interposer, the second electronic die having: a second inner interface comprising a third plurality of ports electrically coupling the second electronic die to the photonic interposer; and a second outer interface comprising a fourth plurality of ports electrically coupling the second electronic die to the photonic interposer, wherein the second outer interface at least partially encloses the second inner interface, wherein the optical network optically couples at least one port of the first inner interface to at least one port of the second inner interface. ### Claim 23 (depends on 22) The computing system of claim 22, wherein each port of the first and second pluralities of ports comprises: an electric connection connecting the first electronic die to the interposer; and a SerDes coupled to the electric connection. ### Claim 24 (depends on 23) The computing system of claim 23, wherein the SerDes is formed on the first electronic die. ### Claim 25 (depends on 22) The computing system of claim 22, wherein at least one port of the first outer interface is positioned within 1 mm of an outer perimeter of the first electronic die. ### Claim 26 (depends on 25) The computing system of claim 25, wherein at least one port of the first inner interface is positioned more than 1 mm away from the outer perimeter of the first electronic die. ### Claim 27 (depends on 22) The computing system of claim 22, wherein the inner interface spans at least 20% of the surface of the electronic die bonded to the photonic interposer.