# US 2024/0201254 A1 · Jitter measuring circuit, jitter analyzing apparatus including the same, and related methods of manufacturing semiconductor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2024/0201254 A1
- Document ID: US20240201254A1
- Status: Published application
- Kind: A1
- Application number: 18/203,024
- Filed: 2023-05-29
- Published: 2024-06-20
- Earliest claimed: 2022-12-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyeon Gwan Oh; Beomsang Yoo
- Web page: https://patentgrep.com/patent/US20240201254A1

## CPC

- G01R 31/31709: {Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901)}
- G01R 29/26: Measuring noise figure; Measuring signal-to-noise ratio
- H10P 72/0604: {Process monitoring, e.g. flow or thickness monitoring}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A jitter analyzing apparatus may include a first delay circuit configured to delay a reference clock to output a first clock, a second delay circuit configured to delay the reference clock to output a second clock having a delay value greater than the first delay circuit, and a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.

## Claims

### Claim 1

A jitter analyzing apparatus comprising:
a first delay circuit configured to delay a reference clock to output a first clock;
a second delay circuit configured to delay the reference clock to output a second clock and have a delay value greater than the first delay circuit; and
a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.

### Claim 2 (depends on 1)

The jitter analyzing apparatus of claim 1, wherein the first delay circuit comprises a plurality of first stages and a number of the plurality of first stages is a first number,
wherein the second delay circuit comprises a plurality of second stages and a number of the plurality of second stages is a second number being greater than the first number, and
wherein each of the plurality of first stages and the plurality of second stages includes a logic gate.

### Claim 3 (depends on 2)

The jitter analyzing apparatus of claim 2, wherein the jitter component includes a jitter component of the logic gate.

### Claim 4 (depends on 3)

The jitter analyzing apparatus of claim 3, wherein the test device is further configured to:
calculate first measurement values by measuring a time at which an edge of the first clock becomes a predetermined level,
calculate second measurement values by measuring a time at which an edge of the second clock becomes the predetermined level, and
measure the jitter component based on a comparison result of the first measurement values and the second measurement values, and a difference between the second number and the first number.

### Claim 5 (depends on 4)

The jitter analyzing apparatus of claim 4, wherein the test device is further configured to measure, as the jitter component, a square root of a value obtained by dividing a difference between a square of a standard deviation of the second measurement values and a square of a standard deviation of the first measurement values by the difference between the second number and the first number.

### Claim 6 (depends on 4)

The jitter analyzing apparatus of claim 4, wherein the test device is further configured to:
calculate third measurement values by measuring a time at which an edge of the reference clock becomes the predetermined level, and
determine whether the first measurement values and the second measurement values are significant, based on a comparison result of the first measurement values and the third measurement values and/or a comparison result of the second measurement values and the third measurement values.

### Claim 7 (depends on 6)

The jitter analyzing apparatus of claim 6, wherein the test device is further configured to determine whether the first measurement values and the second measurement values are significant, based on a difference between a standard deviation of the first measurement values and a standard deviation of the third measurement values and/or a difference between the standard deviation of the second measurement values and a standard deviation of the third measurement values.

### Claim 8 (depends on 3)

The jitter analyzing apparatus of claim 3, wherein the jitter analyzing apparatus is configured to modify a noise model of a transistor included in the first and second delay circuits based on the jitter component.

### Claim 9 (depends on 1)

The jitter analyzing apparatus of claim 1, further comprising:
an impedance matching circuit configured to perform impedance matching in transmission lines configured to transfer the reference clock to the first delay circuit and the second delay circuit; and
an output driver configured to transfer the first clock output from the first delay circuit and the second clock output from the second delay circuit to the test device, and perform impedance matching in transmission lines configured to transfer the first clock and the second clock.

### Claim 10 (depends on 9)

The jitter analyzing apparatus of claim 9, wherein the output driver comprises a plurality of drivers connected in a multi-stage.

### Claim 11

A jitter measuring circuit comprising:
a first delay circuit comprising a plurality of first logic gates connected in series, and configured to output a first clock by delaying a reference clock through the plurality of first logic gates;
a second delay circuit comprising a plurality of second logic gates connected in series, and configured to output a second clock by delaying the reference clock through the plurality of second logic gates, a number of second logic gates being greater than a number of first logic gates;
a first output driver configured to output the first clock to a test device; and
a second output driver configured to output the second clock to the test device,
wherein the jitter measuring circuit is configured to measure a jitter component of a single logic gate of the plurality of first and second logic gates based on the first clock and the second clock.

### Claim 12 (depends on 11)

The jitter measuring circuit of claim 11, wherein each of the plurality of first logic gates and each of the plurality of second logic gates are the same logic gate.

### Claim 13 (depends on 11)

The jitter measuring circuit of claim 11, further comprising:
a first input pad connected to a first transmission line configured to transfer the reference clock;
a second input pad connected to a second transmission line configured to transfer the reference clock;
a first output pad connected to a third transmission line configured to transfer the first clock output from the first output driver to the test device; and
a second output pad connected to a fourth transmission line configured to transfer the second clock output from the second output driver to the test device.

### Claim 14 (depends on 13)

The jitter measuring circuit of claim 13, further comprising:
a first impedance matching circuit connected between the first input pad and the first delay circuit, and configured to perform impedance matching in the first transmission line; and
a second impedance matching circuit connected between the second input pad and the second delay circuit, and configured to perform impedance matching in the second transmission line.

### Claim 15 (depends on 14)

The jitter measuring circuit of claim 14, wherein each of the first impedance matching circuit and the second impedance matching circuit includes a center-tap termination structure.

### Claim 16 (depends on 13)

The jitter measuring circuit of claim 13, wherein each of the first output driver and the second output driver comprises a plurality of drivers connected in multi-stage.

### Claim 17 (depends on 13)

The jitter measuring circuit of claim 13, wherein the first output driver is further configured to perform impedance matching in the third transmission line, and
wherein the second output driver is further configured to perform impedance matching in the fourth transmission line.

### Claim 18

A method of manufacturing a semiconductor device including a jitter analyzing apparatus, the method comprising:
analyzing jitter by using the jitter analyzing apparatus, the analyzing jitter comprising:
outputting a first clock by delaying a reference clock through a first number of logic gates;
outputting a second clock by delaying the reference clock through a second number of logic gates, the second number being greater than the first number;
calculating first measurement values by measuring a time at which an edge of the first clock becomes a predetermined level;
calculating second measurement values by measuring a time at which an edge of the second clock becomes the predetermined level; and
analyzing a jitter component of a single logic gate of the first and second numbers of logic gates based on the first measurement values, the second measurement values, the first number, and the second number.

### Claim 19 (depends on 18)

The manufacturing method of claim 18, wherein the analyzing of the jitter component includes analyzing the jitter component of the single logic gate based on a difference between a square of a standard deviation of the second measurement values and a square of a standard deviation of the first measurement values, and a difference between the second number and the first number.

### Claim 20 (depends on 18)

The manufacturing method of claim 18, further comprising:
forming the semiconductor device by modifying a noise model of a transistor included in the semiconductor device based on the jitter component of the single logic gate.