US 2024/0196631 A1Published application

Memory device structure and fabrication method

AssigneeYangtze Memory Technologies Co., Ltd.

InventorsLiang CHEN, Wei LIU

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Abstract

A method for forming a 3D memory device includes forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one string structure region for forming a string structure; forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one string structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region; forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region; and forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer stacked together.

Claims20

Dependent claims

A method for forming a three-dimensional (3D) memory device, comprising:

forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one string structure region for forming a string structure, including:
forming the plurality of memory cells in the at least one cell region, and forming the string structure in the at least one string structure region;
forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one string structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region, including:
forming HV circuits of a string driver in the at least one string driver region, and forming HV circuits of page buffers in the at least one page buffer HV circuit region;
forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region, including forming low-voltage (LV) circuits of the page buffers in the at least one page buffer region;
and
forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer, wherein the array wafer, the first CMOS wafer, and the second CMOS wafer are stacked together.

4 more elements

A three-dimensional (3D) memory device, comprising:

an array wafer including a first substrate having at least one cell region and at least one string structure region, a plurality of memory cells formed in the at least one cell region, and a string structure formed in the at least one string structure region;
a first complementary metal-oxide-semiconductor (CMOS) wafer including a second substrate having at least one string driver region corresponding to the at least one string structure region and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region, HV circuits of a string driver formed in the at least one string driver region, and HV circuits of page buffers formed in the at least one page buffer HV circuit region;
and
a second CMOS wafer including a third substrate having at least one page buffer region corresponding to the at least one cell region, and low-voltage (LV) circuits of the page buffers formed in the at least one page buffer region;
wherein the array wafer, the first CMOS wafer, and the second CMOS wafer are stacked together.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/089,991Filed 28 Dec 2022
Priority: CN 202211583578.59 Dec 2022
Published: 13 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions