Memory cell array structure having bit line for reducing signal resistance, memory device including the same, and method of forming the same

A memory device, comprising:

• a plurality of memory cells arranged in a first direction, each of the memory cells including a memory element and a transistor having a source terminal coupled to a second electrode of the memory element;
• a bit line coupled to drain terminals of the transistors of the memory cells, the bit line including a first metal line and a second metal line extending in the first direction, the second metal line coupled to the first metal line and disposed over the first metal line in a third direction;
• a plurality of word lines respectively coupled to gate terminals of the transistors of the memory cells, each of the word lines including a third metal line that extends in a second direction crossing the first direction and is disposed over the second metal line in the third direction, the first and the second directions being perpendicular to the third direction;
• and
• a source line coupled to first electrodes of the memory elements of the memory cells,
• wherein the first metal line and the second metal line together carry a bit line signal through the bit line.

A method of forming a memory cell array structure, the method comprising:

• forming a memory cell including a memory element and a transistor having a source terminal coupled to a second electrode of the memory element;
• forming a bit line coupled to a drain terminal of the transistor, the bit line being formed of a first metal line and a second metal line extending in a first direction, the second metal line coupled to the first metal line and formed over the first metal line in a third direction;
• forming a word line coupled to a gate terminal of the transistor, the word line being formed of a third metal line that extends in a second direction crossing the first direction and is formed over the second metal line in the third direction, the first and the second directions being perpendicular to the third direction;
• and
• forming a source line coupled to a first electrode of the memory element,
• wherein the first metal line and the second metal line together carry a bit line signal through the bit line.