Ferroelectric memory device using back-end-of-line (beol) thin film access transistors and methods for forming the same

A memory device comprising:

• metal interconnect structures embedded within dielectric material layers that overlie a substrate;
• an array of thin film transistors embedded within a first dielectric material layer selected from dielectric material layers;
• and
• an array of ferroelectric memory cells embedded within a second dielectric material layer which is selected from the dielectric material layers and is located above, or below, the first dielectric material layer,
• wherein each ferroelectric memory cell within the array of ferroelectric memory cells comprises a respective pillar structure containing a layer stack that includes a first electrode, a ferroelectric dielectric material layer contacting a top surface of the first electrode, and a second electrode contacting a top surface of the ferroelectric dielectric material layer;
• and
• wherein each ferroelectric memory cell within the array of ferroelectric memory cells comprise a respective first node that is electrically connected to a node of a respective thin film transistor within the array of thin film transistors, the respective thin film transistor functioning as an access transistor through a respective subset of the metal interconnect structures.

A method of manufacturing a memory device, the method comprising:

• forming first metal interconnect structures embedded within at least one lower-level dielectric material layer over a substrate;
• forming a thin film transistor over the lower-level dielectric material layer;
• forming a ferroelectric memory cell over the at least one lower-level dielectric material layer prior to, or after, formation of the thin film transistor, wherein the ferroelectric memory cell is formed underneath, above, or at a same level as, a level of the thin film transistor, wherein the ferroelectric memory cell comprises a ferroelectric structure selected from a ferroelectric tunnel junction providing two tunneling resistance values depending on a polarization direction of a ferroelectric material within the ferroelectric dielectric material layer and a programmable ferroelectric capacitor providing two different capacitive states having two different capacitance values depending on the polarization direction of the ferroelectric material within the ferroelectric dielectric material layer;
• and
• forming second metal interconnect structures between the thin film transistor and the ferroelectric memory cell, wherein a subset of the second metal interconnect structures electrically connects a first node of the ferroelectric memory cell to a node of the thin film transistor.