US 2024/0196621 A1 · SEMICONDUCTOR DEVICE, FABRICATION METHOD, AND MEMORY SYSTEM

Abstract

A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.

Claims20

Dependent claims

A semiconductor device, comprising:

a base comprising a first surface defining at least one memory plane region;
and
a stack structure disposed on the first surface and comprising a first portion located at an edge of the memory plane region and a second portion different from the first portion,
wherein the first portion comprises first contact structures penetrating through the stack structure in a first direction and extending to the base;
the second portion comprises second contact structures electrically connected with corresponding gate conductor layers in the stack structure;
and
a top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.

4 more elements

A method for fabricating a semiconductor device, comprising:

alternately stacking first dielectric layers and second dielectric layers in a first direction on a first surface of a substrate to form a dielectric stack structure, wherein the first surface defines at least one memory plane region, the memory plane region comprising a first region located at an edge and a second region different from the first region;
and
forming first contact holes and second contact holes penetrating through the dielectric stack structure in the first direction and extending to the substrate, respectively, in parts of the dielectric stack structure corresponding to the first region and the second region, wherein the first contact holes and the second contact holes are formed from the same mask.

Dependencies are inferred from the claim text.

Facts

Application

18/092,109Filed 30 Dec 2022

Priority

CN 202211596532.79 Dec 2022

Published

13 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Semiconductor device, fabrication method, and memory system

Life of this patent

Semiconductor device, fabrication method, and memory system

Life of this patent

Abstract

Claims20