US 2024/0196615 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorTakuya NISHIKAWA

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Abstract

A semiconductor memory device includes finger structures arranged in a first direction and an inter-finger insulating member disposed between a first finger structure and a second finger structure. The first finger structure includes conductive layers stacked in a stacking direction, a semiconductor column opposed to the conductive layers, a first insulating layer and a second insulating layer covering terrace portions of the conductive layers, and a third insulating layer disposed between the first insulating layer and the inter-finger insulating member in the first direction. The second insulating layer and the third insulating layer have mutually same main components. At least a part of a main component of the first insulating layer is different from the main components of the second insulating layer and the third insulating layer. The second insulating layer and the third insulating layer have mutually different etching rates.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate extending in a first direction and a second direction intersecting with the first direction;
a plurality of finger structures arranged in the first direction and including a first region and a second region arranged in the second direction;
and
an inter-finger insulating member disposed between a first finger structure and a second finger structure adjacent to one another in the first direction among the plurality of finger structures, wherein
the first finger structure includes:
a plurality of conductive layers stacked in a stacking direction intersecting with a surface of the substrate and extending in the second direction across the first region and the second region;
a semiconductor column disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor column;
a plurality of via-contact electrodes disposed in the second region, extending in the stacking direction, and connected to a plurality of terrace portions of the plurality of conductive layers;
a first insulating layer covering the plurality of terrace portions and surrounding outer peripheral surfaces of the plurality of via-contact electrodes;
a second insulating layer covering the plurality of terrace portions via the first insulating layer and surrounding the outer peripheral surfaces of the plurality of via-contact electrodes;
and
a third insulating layer disposed between the first insulating layer and the inter-finger insulating member in the first direction,
the second insulating layer and the third insulating layer have mutually same main components,
at least a part of a main component of the first insulating layer is different from the main components of the second insulating layer and the third insulating layer, and
the second insulating layer and the third insulating layer have mutually different etching rates.

13 more elements

A semiconductor memory device comprising:

a substrate extending in a first direction and a second direction intersecting with the first direction;
a plurality of finger structures arranged in the first direction and including a first region and a second region arranged in the second direction;
and
an inter-finger insulating member disposed between a first finger structure and a second finger structure adjacent to one another in the first direction among the plurality of finger structures, wherein
the first finger structure includes:
a plurality of first conductive layers stacked in a stacking direction intersecting with a surface of the substrate and extending in the second direction across the first region and the second region;
a first semiconductor column disposed in the first region, extending in the stacking direction, and opposed to the plurality of first conductive layers;
a first electric charge accumulating film disposed between the plurality of first conductive layers and the first semiconductor column;
a plurality of first via-contact electrodes disposed in the second region, extending in the stacking direction, and connected to a plurality of terrace portions of the plurality of first conductive layers;
and
a first insulator structure covering the plurality of terrace portions and surrounding outer peripheral surfaces of the plurality of first via-contact electrodes,
a surface on a side of the second finger structure in the first direction of the first insulator structure includes:
a first part extending in the stacking direction along the inter-finger insulating member;
and
a second part disposed between the first part and the plurality of first conductive layers, and
a first end portion on an opposite side of the plurality of first conductive layers in the stacking direction of the second part is disposed at a position farther from the second finger structure in the first direction than a second end portion on a side of the plurality of first conductive layers in the stacking direction of the first part.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/461,827Filed 6 Sep 2023
Priority: JP 2022-1965808 Dec 2022
Published: 13 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout