Semiconductor memory devices

A semiconductor memory device comprising:

• a substrate including a plurality of active regions in a memory cell region and a peripheral active region in a peripheral region;
• a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region;
• a plurality of buried contacts respectively and electrically connected to the plurality of active regions, the plurality of buried contacts partially filling a space between the plurality of bit line structures;
• a plurality of lower landing pads in the space between the plurality of bit line structures and respectively on the plurality of buried contacts;
• a landing pad insulating structure in contact with the plurality of bit line structures and the plurality of lower landing pads, the landing pad insulating structure including a plurality of landing pad holes;
• a plurality of upper landing pads respectively filling the plurality of landing pad holes and respectively connected to the plurality of lower landing pads;
• a gate line in the peripheral region;
• a peripheral bit line insulating structure on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses;
• and
• a plurality of peripheral bit lines respectively filling the plurality of peripheral bit line recesses,
• wherein a top surface of each of the plurality of upper landing pads, a top surface of the landing pad insulating structure, a top surface of each of the plurality of peripheral bit lines, and a top surface of the peripheral bit line insulating structure are coplanar with one another at the same vertical level.

A semiconductor memory device comprising:

• a substrate including a plurality of active regions in a memory cell region and a peripheral active region in a peripheral region;
• a plurality of word lines respectively in a plurality of word line trenches in the substrate, the plurality of word line trenches extending in parallel with each other in a first horizontal direction in the memory cell region;
• a plurality of bit line structures extending on the plurality of word lines in parallel with each other in a second horizontal direction that is perpendicular to the first horizontal direction, wherein each of the plurality of bit line structures includes a bit line, an insulating capping line covering the bit line, and a pair of insulating spacer structures respectively covering opposite side walls of each of the bit line and the insulating capping line;
• a plurality of buried contacts respectively and electrically connected to the plurality of active regions, the plurality of buried contacts partially filling a space between the plurality of bit line structures;
• a plurality of lower landing pads in the space between the plurality of bit line structures and respectively on the plurality of buried contacts;
• a landing pad insulating structure in contact with the plurality of bit line structures and the plurality of lower landing pads, the landing pad insulating structure including a plurality of landing pad holes;
• a plurality of upper landing pads respectively filling the plurality of landing pad holes and respectively connected to the plurality of lower landing pads;
• a plurality of capacitor structures including a plurality of lower electrodes respectively and electrically connected to the plurality of upper landing pads, an upper electrode, and a capacitor dielectric layer between the plurality of lower electrodes and the upper electrode;
• a gate line in the peripheral region;
• a filling insulation layer in the peripheral region, the filling insulation layer covering the substrate and the gate line and including a plurality of contact holes;
• a plurality of contact plugs respectively filling the plurality of contact holes and electrically connected to the peripheral active region;
• a peripheral bit line insulating structure on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses in communication with the plurality of contact holes, respectively;
• and
• a plurality of peripheral bit lines respectively filling the plurality of peripheral bit line recesses and electrically connected to the plurality of contact plugs,
• wherein the landing pad insulating structure includes a plurality of insulating grooves in a lower portion thereof, the plurality of insulating grooves being respectively filled with the plurality of bit line structures, and
• the plurality of peripheral bit lines pass through the peripheral bit line insulating structure and extend inside an upper portion of the filling insulation layer.