Semiconductor device

A semiconductor device, comprising:

• an active pattern disposed on a substrate;
• an isolation pattern disposed on the substrate, wherein the isolation pattern covers a sidewall of the active pattern;
• a gate structure disposed on an upper portion of the active pattern and an upper portion of the isolation pattern, wherein the gate structure extends in a first direction substantially parallel to an upper surface of the substrate;
• an insulation pattern structure disposed on the active pattern, the isolation pattern and the gate structure;
• a bit line structure extending on the active pattern and the insulation pattern structure in a second direction, wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction, and wherein the bit line structure includes a first conductive pattern structure, a second conductive pattern and an insulation structure sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate;
• a lower spacer structure disposed on a lower portion of a sidewall of the bit line structure, and including a first spacer, a second spacer and a third spacer;
• an upper spacer structure disposed on the lower spacer structure and on an upper portion of the sidewall of the bit line structure;
• a contact plug structure disposed on the active pattern, and spaced apart from the bit line structure;
• and
• a capacitor disposed on the contact plug structure,
• wherein the first conductive pattern structure includes a lower portion, a middle portion and an upper portion sequentially stacked on each other in the vertical direction, and
• wherein a first width, in the first direction, of the lower portion of the first conductive pattern structure is greater than a second width, in the first direction, of the middle portion of the first conductive pattern structure.

A semiconductor device, comprising:

• an active pattern disposed on a substrate;
• a gate structure disposed on an upper portion of the active pattern;
• a bit line structure disposed on the active pattern, wherein the bit line structure includes a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a lower spacer structure disposed on a lower portion of a sidewall of the bit line structure;
• an upper spacer structure disposed on the lower spacer structure, and disposed on an upper portion of the sidewall of the bit line structure;
• a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure;
• and
• a capacitor disposed on the contact plug structure,
• wherein the first conductive pattern includes:
• a lower portion contacting an upper surface of the active pattern;
• a middle portion disposed on the lower portion;
• and
• an upper portion disposed on the middle portion,
• wherein the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices, and
• wherein the lower spacer structure covers sidewalls of the lower portion and the middle portion of the first conductive pattern, and the upper spacer structure covers a sidewall of the upper portion of the first conductive pattern.