Semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorJunhyeok Ahn
Life of this patent
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Abstract
A semiconductor memory device may include an active pattern on a substrate and at least partially surrounded by a device isolation pattern, a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode including lower and upper portions, and a side-capping pattern on a top surface of the lower portion of the gate electrode. The side-capping pattern may be on a side surface of the upper portion of the gate electrode, and a top surface of the side-capping pattern may be located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.
Claims20
A semiconductor memory device, comprising:
- an active pattern on a substrate and at least partially surrounded by a device isolation pattern;
- a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode comprising lower and upper portions;
- and
- a side-capping pattern on a top surface of the lower portion of the gate electrode,
- wherein the side-capping pattern is on a side surface of the upper portion of the gate electrode, and
- wherein a top surface of the side-capping pattern is located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.
A semiconductor memory device, comprising:
- an active pattern on a substrate and at least partially surrounded by a device isolation pattern;
- a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode comprising lower and upper portions;
- a gate insulating pattern that extends into a space between the gate electrode and the active pattern;
- and
- a side-capping pattern between the upper portion of the gate electrode and the gate insulating pattern,
- wherein a top surface of the side-capping pattern is located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.
A semiconductor memory device, comprising:
- an active pattern on a substrate and at least partially surrounded by a device isolation pattern;
- a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode comprising lower and upper portions;
- a gate capping pattern on a top surface of the upper portion of the gate electrode;
- and
- a side-capping pattern on a side surface of the upper portion of the gate electrode,
- wherein the side-capping pattern is between the gate capping pattern and the lower portion of the gate electrode, and
- wherein a top surface of the side-capping pattern is located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.
Dependencies are inferred from the claim text.