Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate, a plurality of memory chips, a controller, a plurality of terminals, a sealing member, and a sheet. The substrate has a first plane and a second plane positioned on an opposite side of the first plane. The plurality of memory chips are mounted on the first plane of the substrate. The controller is mounted on the first plane of the substrate to control the plurality of memory chips. The plurality of terminals provided on the second plane of the substrate and including a plurality of test terminals. The sealing member seals the first plane of the substrate, the plurality of memory chips, and the controller. The sheet covers the plurality of test terminals among the plurality of terminal. The sheet is an insulator and has a thermal conductivity of from 1.0 W/(m·K) to 8.0 W/(m·K).

Dependencies are inferred from the claim text.