Asynchronous bit detection mechanism for ask demodulators

A method for decoding a biphase mark coding (BMC) encoded signal, the method comprising:

• generating, by a matched filter, a first response and a second response to the BMC encoded signal, the first response and second response operating, respectively, at a half clock period and a full clock period of the BMC encoded signal;
• generating, by a detector circuit coupled to the matched filter, an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response;
• and
• decoding the BMC encoded signal, by a finite state machine (FSM) circuit, based on the output signal of the detector circuit.

An amplitude shift keying (ASK) demodulator for decoding a biphase mark coding (BMC) encoded signal, the ASK demodulator comprising:

• a matched filter configured to generate a first response and a second response to the BMC encoded signal, the first response and second response operating, respectively, at a half clock period and a full clock period of the BMC encoded signal;
• a detector circuit coupled to an output of the matched filter, the detector circuit configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response;
• and
• a finite state machine (FSM) circuit configured to decode the BMC encoded signal based on the output signal of the detector circuit.