IC With Delay-Locked Loop With Widened Lock Range
AssigneeSambaNova Systems, Inc.
InventorsFahim ur RAHMAN, Jinuk SHIN
Life of this patent
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Abstract
An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.
Claims14
An integrated circuit (IC) comprising a delay-locked loop (DLL) with a DLL signal input, the DLL comprising:
- a delay line including a series of delay stages, with a signal input coupled with the DLL signal input, a speed control input, a first phase output, and a second phase output;
- a gater with a first gater input coupled with the first phase output and a second gater input coupled with the second phase output, a gater clock input coupled with the DLL signal input, a first gater output and a second gater output;
- a phase-frequency detector (PFD) with a first PFD input coupled with the first gater output and a second PFD input coupled with the second gater output, and a first PFD output and a second PFD output;
- and
- a loop filter with a first input coupled with the first PFD output and a second input coupled with the second PFD output, and a speed control output coupled with the speed control input.
Dependencies are inferred from the claim text.