Output buffer circuit

A circuit comprising:

• a first set of transistors which receive an input signal and at least one voltage reference signal and outputs at least one level shifted output signal;
• a second set of transistors which receive one of the at least one level shifted output signal and outputs at least one pre-driver output signal;
• at least one delay circuit connected to a gate of a first device of the second set of transistors and between a drain and a source of adjacent devices of the first set of transistors;
• and
• a third set of transistors which receive one of the at least one pre-driver output signal and outputs a main driver output signal,
• wherein the at least one delay circuit comprises two delay circuits,
• a first delay circuit of the two delay circuits is connected between the drain of a first PFET device, a source of a second PFET device of the first set of transistors and a gate of a first PFET device of the second set of transistors, and
• a second delay circuit of the two delay circuits is connected between a drain of a first NFET device, a source of a second NFET device and a gate of a third NFET device of the second set of transistors.

A method comprising:

• performing a level shifting operation of an output buffer circuit to level shift an input to the output buffer circuit;
• performing a pre-driving operation of the output buffer circuit to delay the level shifted input;
• and
• performing a main driving operation of the output buffer circuit to output a main driver output signal based on the delayed level shifted input.

A structure comprising:

• a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal;
• a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit comprising at least one delay circuit;
• and
• a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal, wherein:
• the level shifter circuit and the pre-driver circuit each comprises a first set a plurality of PFET devices and a plurality of NFET devices;
• at the level shifter circuit:
• a first PFET device receives a supply voltage signal at its source;
• and
• a second PFET device receives a voltage reference PFET signal of the at least one voltage reference signal at its gate;
• and
• the at least one delay circuit is connected between a drain of the first PFET device and a source of the second PFET device,
• wherein the at least one delay circuit comprises two delay circuits, a first delay circuit of the two delay circuits is connected between the drain of the first PFET device, a source of the second PFET device and a gate of a first PFET device of the pre-driver circuit, and a second delay circuit of the two delay circuits is connected between a drain of a first NFET device, a source of a second NFET device and a gate of a third NFET device of the pre-driver circuit.