Apparatus and method for monitoring duty cycle of memory clock signal
AssigneeElectronics and Telecommunications Research Institute
InventorsMin-Hyung CHO, Yi-Gyeong KIM, Su-Jin PARK, Young-Deuk JEON
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Abstract
Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
Claims13
An apparatus for monitoring a duty cycle of a memory clock signal, comprising:
- a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal;
- and
- a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
A method for monitoring a duty cycle of a memory clock signal, comprising:
- generating a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a waveform of the first monitoring target clock signal;
- and
- measuring a pulse width of the second monitoring target clock signal using a reference clock signal.
A device for converting a frequency of a duty cycle monitoring target clock signal, wherein:
- the device is configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and
- the device comprises one or more half clock generators connected in cascade, each of the half clock generators being configured to output a clock signal by decreasing a frequency of an input clock signal to half while maintaining a duty cycle of the input clock signal.
Dependencies are inferred from the claim text.