Semiconductor package antenna structure and its manufacturing method

A manufacturing method for the semiconductor package antenna structure, comprising the following steps:

• forming a first substrate, which includes sequentially forming at least two layers of first redistribution layer, embedding a chip within these at least two layers of first redistribution layer during the process of forming at least two layers of the first redistribution layer, wherein an active surface of the chip is electrically coupled with one of the first redistribution layers;
• forming a second substrate, which includes forming a second redistribution layer and forming a second conductive pillar layer protruding from the second redistribution layer, wherein the active surface of the chip faces away from the second substrate;
• and
• bonding the first substrate with the second substrate, wherein the second conductive pillar layer is connected to the second substrate and an air dielectric layer is formed between the second redistribution layer, the second conductive pillar layer, and the first substrate;
• wherein a part of the first redistribution layer, a part of the second redistribution layer, and a part of the second conductive pillar layer form a transmitting antenna, while another part of the first redistribution layer, another part of the second redistribution layer, and another part of the second conductive pillar layer form a receiving antenna.

A manufacturing method for the semiconductor package antenna structure, comprising:

• forming a first substrate, which includes sequentially forming at least two layers of first redistribution layer, embedding a chip within these at least two layers of first redistribution layer during the process of forming at least two layers of the first redistribution layer, wherein an active surface of the chip faces away from the second substrate, and it is electrically coupled with one of the first redistribution layers;
• forming a second substrate on the first substrate that comprises:
• forming a first seed layer on the first substrate;
• forming a photoresist layer, which has at least one first through hole, on the first seed layer;
• electroplating to form a second conductive pillar layer in the first through hole;
• forming a second redistribution layer to connect to the second conductive pillar layer;
• and
• removing the photoresist layer to form an air dielectric layer between the second redistribution layer, the second conductive pillar layer, and the first substrate;
• and
• wherein the active surface of the chip faces away from the second substrate;
• wherein a part of the first redistribution layer, a part of the second redistribution layer, and a part of the second conductive pillar layer form a transmitting antenna, while another part of the first redistribution layer, another part of the second redistribution layer, and another part of the second conductive pillar layer form a receiving antenna.