Field effect transistor

A field effect transistor, comprising:

• a substrate;
• a first nitride semiconductor layer, disposed over the substrate;
• a second nitride semiconductor layer, disposed on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer;
• a plurality of source electrodes on the second nitride semiconductor layer, respectively extending along a first direction, and arranged in parallel with each other along the first direction and a second direction perpendicular to the first direction in a plan view;
• a plurality of drain electrodes, on the second nitride semiconductor layer, respectively extending along the first direction, arranged in parallel with each other along the first direction and the second direction, and alternately arranged with the plurality of source electrodes along the second direction;
• a plurality of gate structures, on the second nitride semiconductor layer, respectively extending along the first direction, arranged in parallel with each other along the first direction and the second direction, and respectively surrounding one of the plurality of source electrodes in the plan view, wherein each of the plurality of gate structures includes:
• a third nitride semiconductor layer disposed on the second nitride semiconductor layer;
• and
• a gate electrode disposed on the third nitride semiconductor layer,
• a first high resistance region, disposed in the first nitride semiconductor layer and the second nitride semiconductor layer and between the adjacent drain electrodes along the first direction;
• a plurality of gate connection portions, respectively electrically connecting the adjacent gate structures along the first direction;
• a gate wiring, located above the first high resistance region, electrically connected to the plurality of gate connection portions and extending along the second direction;
• and
• an insulating layer, covering the plurality of source electrodes, the plurality of drain electrodes, the plurality of gate structures and the plurality of gate connection portions, wherein the insulating layer is disposed between the gate wiring and the first high resistance region.