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US 2024/0194758 A1Published application
Gate all around transistor with dual inner spacers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
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Abstract
A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
Claims20
A method, comprising:
- forming a first channel of a transistor;
- forming a second channel of the transistor above the first channel;
- forming a sheet inner spacer of a first composition between channel and the second channel;
- forming a cladding inner spacer of a second composition different than the first composition in contact with the first channel and the second channel;
- forming a gate metal of the transistor wrapped around the first channel and the second channel;
- and
- forming a source/drain region in contact with the first channel and the second channel and separated from the gate metal in a first lateral direction, wherein the sheet inner spacer is positioned between the gate metal and the source/drain region and has a first lateral thickness in the first direction, wherein the cladding inner spacer is positioned between the gate metal and the source/drain region and has a second lateral thickness in the first direction greater than the first lateral thickness.
4 more elements
A method, comprising:
- forming a plurality of stacked channels of a transistor;
- forming, with a first deposition process, a plurality of sheet inner spacers each between a respective pair of the channels
- forming, with a second deposition process, a cladding inner spacer in contact with each of the channels and the sheet inner spacers;
- forming a source/drain region of the transistor in contact with the channels, the sheet inner spacers, and the cladding inner spacer;
- depositing a gate dielectric of the transistor on the channels and on the sheet inner spacers;
- and
- depositing a gate metal of the transistor on the gate dielectric and between the channels, wherein the cladding inner spacer is thicker than the sheet inner spacers in a lateral direction separating the gate metal from the source/drain region.
4 more elements
An integrated circuit, comprising:
- a gate all around transistor, the gate all around transistor including:
- a source/drain region;
- a first channel;
- a second channel above the first channel;
- a cladding inner spacer extending vertically and in contact with the source/drain region, the first channel, and the second channel;
- a sheet inner spacer between the first channel and the second channel and in contact with the first channel, the second channel, the cladding inner spacer and the source/drain region, wherein the cladding inner spacer and the sheet inner spacers are different dielectric materials;
- a gate dielectric positioned on the first channel and the second channel;
- and
- a gate metal positioned on the gate dielectric and wrapped around the first channel and the second channel and separated from the source/drain region by the cladding inner spacer and the sheet inner spacer.
6 more elements
Dependencies are inferred from the claim text.