Vertical self aligned gate all around transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Xuan HUANG, Hou-Yu CHEN, Cheng-Ting CHUNG, Jin CAI
Life of this patent
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Abstract
A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.
Claims20
A method, comprising:
- forming, in a stack of semiconductor layers over a lower source/drain region of a first vertical transistor, a trench adjacent to a channel region of the first vertical transistor;
- exposing a portion of the channel region by selectively removing, via the trench with a first etching process, a first layer of the stack with respect to a second layer of the stack;
- forming an upper inner spacer in contact with the channel region in place of the first layer;
- removing the second layer of the stack via the trench with a second etching process;
- forming a gate metal in place of the second layer;
- and
- forming an upper source/drain region of the first vertical transistor on the channel region and the upper inner spacer.
A method, comprising:
- forming a first channel region of a first vertical transistor extending vertically from a first lower source/drain region of the first vertical transistor;
- forming a first lower inner spacer in contact with the first channel region;
- forming, in a same deposition process as the first lower inner spacer, a first upper inner spacer above the first lower inner spacer and in contact with the first channel region;
- after forming the first lower and upper inner spacers, forming a gate dielectric on a top of the first lower inner spacer, on a sidewall of the first channel region between the first upper and lower inner spacers, and on a bottom of the first upper inner spacer;
- depositing a gate metal between the first upper and lower inner spacers;
- and
- forming an upper source/drain region of the first vertical transistor in contact with a top of the first channel region and a top of the first upper inner spacer.
A device, comprising:
- a first vertical transistor, including:
- a first lower source/drain region;
- a first channel region extending vertically from the first lower source/drain region;
- a first lower inner spacer in contact with the first channel region and the first lower source/drain region;
- and
- a first gate electrode positioned on the first lower inner spacers and laterally surrounding the first channel region;
- a shallow trench isolation region in contact with the first lower source/drain region;
- and
- an interlevel dielectric layer extending vertically from the shallow trench isolation region and in contact with sidewalls of the first lower inner spacer and the first gate electrode.
Dependencies are inferred from the claim text.