Semiconductor device

A semiconductor device comprising:

• a substrate;
• an active pattern disposed on the substrate and extending in a first direction;
• a plurality of gate electrodes covering the active pattern and extending in a second direction, the second direction intersecting the first direction;
• a plurality of gate spacers, each being disposed on a sidewall of each of the plurality of gate electrodes;
• a first gate capping film disposed on the each of the plurality of gate electrodes and the each of the plurality of gate spacers;
• a source/drain pattern disposed between adjacent ones of the plurality of gate electrodes;
• an etch stop film disposed along a sidewall of the each of the plurality of gate spacers and a profile of the source/drain pattern;
• a liner film extending along a profile of the etch stop film, a sidewall of the first gate capping film, and an upper surface of the first gate capping film, wherein at least a portion of the liner film is disposed in the source/drain pattern;
• a second gate capping film disposed on the liner film and overlapping the first gate capping film in a third direction, the third direction intersecting the first direction and the second direction;
• and
• a source/drain contact disposed between the adjacent ones of the plurality of gate electrodes and connected to the source/drain pattern,
• wherein the liner film includes an oxide-based insulating material.

A semiconductor device comprising:

• a substrate;
• an active pattern disposed on the substrate, wherein the active pattern includes a lower pattern extending in a first direction, and at least one sheet pattern spaced apart from the lower pattern in a third direction, the third direction intersecting the first direction;
• a field insulating film covering a sidewall of the lower pattern;
• a plurality of gate electrodes disposed on the lower pattern and covering the at least one sheet pattern, wherein each of the plurality of gate electrodes extends in a second direction, the second direction intersecting the first direction and the third direction;
• a plurality of gate spacers, each being disposed on a sidewall of the each of the plurality of gate electrodes;
• a plurality of gate capping films respectively disposed on the plurality of gate electrodes;
• a source/drain pattern disposed between adjacent ones of the plurality of gate electrodes, and connected to the at least one sheet pattern;
• an etch stop film disposed along an upper surface of the field insulating film, a sidewall of the each of the plurality of gate spacers, and a profile of the source/drain pattern;
• an interlayer insulating film disposed between the adjacent ones of the plurality of gate electrodes, wherein a contact trench exposing the source/drain pattern is defined in the interlayer insulating film;
• a liner film disposed on an outer sidewall of the contact trench;
• and
• a source/drain contact disposed on the liner film, and filling the contact trench, wherein the source/drain contact is connected to the source/drain pattern,
• wherein a vertical level of a bottom surface of the source/drain contact based on an upper surface of the substrate is lower than a vertical level of a bottom surface of the liner film based on the upper surface of the substrate,
• wherein the etch stop film includes a nitride-based insulating material,
• wherein the liner film includes an oxide-based insulating material, and
• wherein at least a portion of the liner film is in contact with the source/drain pattern.